1 Razor: A Low Power Processor Design Presented By: - Murali Dharan.

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Presentation transcript:

1 Razor: A Low Power Processor Design Presented By: - Murali Dharan

T. Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp Power Aware Computing Primary concern in design of processors and SoCs Primary concern in design of processors and SoCs Paradox of need of higher clock frequencies and low power designs Paradox of need of higher clock frequencies and low power designs f α V dd E = SCV 2 dd + V dd I leak T

D. Ernst, et al., "Razor: A Low-Power Pipeline Based on Circuit- Level Timing Speculation," Proc. 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003, pp.7 3 Solution Dynamic Voltage Scaling (DVS) Dynamic Voltage Scaling (DVS) Periods of low processor utilization exploited by lowering clock frequency Periods of low processor utilization exploited by lowering clock frequency Critical supply voltage Critical supply voltage Min. supply voltage resulting in correct operation Min. supply voltage resulting in correct operation Should be sufficient to factor in global and local variations Should be sufficient to factor in global and local variations

T. Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp Voltage Margins Process Margin Process Margin Result from manufacturing variations Result from manufacturing variations Ambient Margin Ambient Margin Slower circuit operations at higher temperatures Slower circuit operations at higher temperatures Noise Margin Noise Margin Safeguard against different noise sources Safeguard against different noise sources

D. Ernst, et al., "Razor: A Low-Power Pipeline Based on Circuit- Level Timing Speculation," Proc. 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003, pp Basic Idea Proposed Tune the supply voltage by monitoring the error rate during operation Tune the supply voltage by monitoring the error rate during operation Accounts for both global and local variations Accounts for both global and local variations Eliminates need for “Voltage Margins” Eliminates need for “Voltage Margins” Sub critical voltage cause trade off between error recovery and power savings Sub critical voltage cause trade off between error recovery and power savings Savings up to 64.2% with penalty of <3% Savings up to 64.2% with penalty of <3%

Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp Implementation of Error Correction

Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp Experimental Results

Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp Prototype Implementation

Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp Energy Optimal Characteristics

Todd Austin et al., "Making Typical Silicon Matter with Razor," IEEE Computer, March 2004, pp Future Research Areas Implementation of Razor Technology in the design of Control Logics Implementation of Razor Technology in the design of Control Logics Implementation of Razor Technology in the design of Memories Implementation of Razor Technology in the design of Memories

11 References “Making Typical Silicon Matter with Razor” “Making Typical Silicon Matter with Razor” Todd Austin, David Blaauw, Trevor Mudge University of Michigan; Krisztián Flautner ARM Ltd. Todd Austin, David Blaauw, Trevor Mudge University of Michigan; Krisztián Flautner ARM Ltd. “Razor: A Low Power Pipeline Based on Circuit-Level timing Speculation” “Razor: A Low Power Pipeline Based on Circuit-Level timing Speculation” Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge Advanced Computer Architecture Lab University of Michigan and Krisztián Flautner ARM Ltd. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge Advanced Computer Architecture Lab University of Michigan and Krisztián Flautner ARM Ltd. IEEE Spectrum Feb Edition “Intel and ARM are Exploring Self-Correction Schemes to Boost Processor Performance and Cut Power” by Neil Savage IEEE Spectrum Feb Edition “Intel and ARM are Exploring Self-Correction Schemes to Boost Processor Performance and Cut Power” by Neil Savage