CHDStd and Related Standards Efforts

b Technology Trend The Physics Decreasing Gate Length  50 m transistors by 2000 Increased file & file sizes Increased Power Decreasing Metal Pitch  GHz range in by 1999 Coupled effects Reliability issues Decreasing Clock Cycle  GHz range by 1999 Inductive effects Reflections The Physics of Small

Density Frequency Analysis Time  to Design Change (design cycle time) Minimize Data Redundancy (data management) Maximize Design Reuse (productivity) Minimize File Translation (cycle time) Full Scope Model (complex analysis) Common Analysis Engine (convergence) Concurrent Design and Analysis (cycle time) Supplier Technology Characterizations (accuracy) Harness the Physics of Small Ability to integrate tools of choice

Goals  Develop an open industry wide model for chip design and analysis data (CHDStd) - comprehensive data scope and unambiguous API access  Demonstrate value proposition with SEMATECH companies  Achieve commercial adoption of database servers and EDA applications using the specification  Gain formal standards accreditation  Develop an open industry wide model for chip design and analysis data (CHDStd) - comprehensive data scope and unambiguous API access  Demonstrate value proposition with SEMATECH companies  Achieve commercial adoption of database servers and EDA applications using the specification  Gain formal standards accreditation

CHDStd Elements IDM API Layout Electrical Physical Netlist Design Library Electrical Specs. Constraints Layer Rules Wire/Via/Pad Models PDL API Process Library Physical Properties Function Power Delay OLA API Cell Library Hw/Sw Logic Circuit Place Wire other Perf Timing Power Noise Test other Common Datamodel Concurrent Comm. DesignAnalyze

Methodology EDA Applications Common Data Access Data Repository Flow & Data Management CHDStd Effective Integration of All

CHDStd  Comprehensive Data Scope –Design Library (IDM) hierarchical connectivity network for the design physical characteristics (wires, shapes, area, placement, constraints, etc.) electrical characteristics (parasitics, delays, constraints, etc.) –Technology Library (OLA) delay and power calculation, logic function, block attributes cell physical properties (OLA-P) –Process Definition Library (PDL) physical and electrical models, design rules, constraints process characterization (SIPPs) –Engineering Change Order (ECO) language  Full Application Program Interface (API)  Comprehensive Data Scope –Design Library (IDM) hierarchical connectivity network for the design physical characteristics (wires, shapes, area, placement, constraints, etc.) electrical characteristics (parasitics, delays, constraints, etc.) –Technology Library (OLA) delay and power calculation, logic function, block attributes cell physical properties (OLA-P) –Process Definition Library (PDL) physical and electrical models, design rules, constraints process characterization (SIPPs) –Engineering Change Order (ECO) language  Full Application Program Interface (API)

Interface PhysicalConstraints FoldedOccurrence Views Netlist Load/Save Layout Persistent Store Hierarchical Selectable Incremental Electrical Design Library (IDM) PlacementWiring

IDM Highlights  Proven –Based on technology in use at IBM  Extensible –Property, Group, Rule Box  Hierarchical –Full hierarchy preserved on both folded and occurrence models  Incremental –Application selectable data and views –Formal mechanisms defined for incremental support  Concurrent –Facilities to manage EDA design and analysis applications working on same design library concurrently, reducing costly sequential steps  Proven –Based on technology in use at IBM  Extensible –Property, Group, Rule Box  Hierarchical –Full hierarchy preserved on both folded and occurrence models  Incremental –Application selectable data and views –Formal mechanisms defined for incremental support  Concurrent –Facilities to manage EDA design and analysis applications working on same design library concurrently, reducing costly sequential steps

Cell Library (OLA)  Open Library API - simple cells through complex cores –Delay and Power calculations –Block function –Block characteristics used for Synthesis, Test, etc. –Block Physical characteristics Based on LEF Data Model  Direct Access Compiled IP Protection Speed Size  ASCII Equivalent (ALF) from OVI Diagnosis and repair  Based on DPCS (IEEE 1481) Architecture  Open Library API - simple cells through complex cores –Delay and Power calculations –Block function –Block characteristics used for Synthesis, Test, etc. –Block Physical characteristics Based on LEF Data Model  Direct Access Compiled IP Protection Speed Size  ASCII Equivalent (ALF) from OVI Diagnosis and repair  Based on DPCS (IEEE 1481) Architecture

OLA - Physical  Adds cell physical characterization to OLA –Extended OLA API –Extended ALF file format  Based on proven LEF data model  Transfer of LEF format from Cadence to enhance migration  Adds cell physical characterization to OLA –Extended OLA API –Extended ALF file format  Based on proven LEF data model  Transfer of LEF format from Cadence to enhance migration

OLA-Physical TranslateCompile API DCL ALF Timing Power Function Physical Reader Ttranslate DPCM LEF EDA Apps Migration Strategic- Field Repair Strategic- Flow Today

Technology/Package Wiring layers Placement area Wiring area I/O area Terminal placement Wiring models & constraints Via models Power models & constraints Placement models & constraints Pre-placed structuresTechnology/Package Wiring layers Placement area Wiring area I/O area Terminal placement Wiring models & constraints Via models Power models & constraints Placement models & constraints Pre-placed structures Application Areas Placement Power Application Areas Placement Power Constraints Cell size, placement and wiring porosity,.. Net - length, resistance, capacitance, delay,.. Port and wiring constraintsConstraints Cell size, placement and wiring porosity,.. Net - length, resistance, capacitance, delay,.. Port and wiring constraints Process Definition Library (PDL)  Describes technology characteristics and constraints –Technology design groundrules –Chip background and image descriptions –Design constraints  Describes technology characteristics and constraints –Technology design groundrules –Chip background and image descriptions –Design constraints

SIPPs  A single technology characterization –Tool-independent –Electrically accurate –Flexible for different abstraction levels –Extensible enough for future processes technology  Advantages –Supplier characterizes process in one format –Tools have standard access to characterization Designer gets better correlation of results –Design can use multiple extractors in flow Allowing selective accuracy vs. speed tradeoffs  Based on technology from Frequency Technology and OEA international  A single technology characterization –Tool-independent –Electrically accurate –Flexible for different abstraction levels –Extensible enough for future processes technology  Advantages –Supplier characterizes process in one format –Tools have standard access to characterization Designer gets better correlation of results –Design can use multiple extractors in flow Allowing selective accuracy vs. speed tradeoffs  Based on technology from Frequency Technology and OEA international

T D j+2 CDL Rs KjKj swcov j+1 Rvia Vw mingap j Edge K j+3 K j+2 SIPPs Physical Model Concept Layer by Layer Description of substrate, dielectrics, and metal Metal dimensions and resistivities Dielectric thicknesses and permitivity Metal and trench coatings Dimension losses Air gaps Temperature and spacing variations Process variations

CHDStd Plug and Play

Integration Use Models Application Integrated Functions. Interfaced Functions Translate Application Operational Memory or Data Repository Application (Private Model) Map CHDStd API API is point of integration rather than translated files Application (Private Model)

CHDStd Reference Server Add Delete Traverse API Load Save API Application File Repository Memory Structures

Reference Server Use Model Options Add Delete Traverse API Load Save API Application File Repository Memory Structures Add Delete Traverse API Load Save API Application File Repository Add Delete Traverse API Load Save API Application File Repository Memory Structures Memory Structures CHDStd Reference Server Customer Developed Server Reference API with Customer Repository

Net addNet deleteNet reconnectNet Cell addCell deleteCell moveCell swapCells disconnectCell Port addPort deletePort movePort swapPorts connectPort disconnectPort Other changeChildDef updateCellProperty updatePortProperty updateNetProperty Engineering Change Orders (ECO)  Defines delta modifications to a design –Add, delete and modify cells, ports or nets as well as their placement and properties  Allows incremental design changes between sessions and across design teams  Facilitates managed EC process across the design team  Defines delta modifications to a design –Add, delete and modify cells, ports or nets as well as their placement and properties  Allows incremental design changes between sessions and across design teams  Facilitates managed EC process across the design team

Transistor Level Timing Analysis Design Model IDM Synthesis Timing Design Planner Cell Library Process Variation Modeler Design Library Power Network Analysis Signal Integrity Verification Delay Power Function Physical IEEE 1481 Extractor(s) Putting it Together - CHDStd Place & Route Technology/Process Parameters PDL Process Library OLA

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