Elektronics - Hephy Vienna M.PernickaM.FriedlC.IrmlerJ.PirkerS.SchmidSteininger C. Schwanda + Involved in BELLE and CMS ADC system with 36 inputs and data processors Possibility to further reduce the occupancy using APV25 Test results where we want to prove the performance Some remarks to the APV25 and read out system

APV inputs peaking, shaping time adjustable, min < 50 ns, S/N ? Works up to 80 Mhz, tested but not absolute, could depends of the waver Minimum delay for 2 trigger 3 clocks Delay up to 160 clocks Multi event buffer 32 places with single hit read out 2 Modes for single hit read out. Peak mode or deconvolution mode. ( only 40 MHz) Analog Pulse Shape Processor Calibration system, 8 steps for one clock, max charge 25 fC Read out speed: clock or half clock, for seen for data multiplexing at CMS Radiation hard 2.5, 1.25 Volt supply

We can adjust by I2C commands: Apv25 gets an external address A: the filter curve by changing the bias current for amplifier and shaper and the value of the feed back resistors. B: With or without inverter. P or n side of the detector C: The pipe line steps and there for the trigger delay max. 160*clock D: Peaking- or deconvolution mode, E. from one input signal one or 3 signals, single or multi hit mode E: Gain for the output signal F Analogue value and delay for the calibration signal

Output signal for a APV25 for 2 trigger in a short time distance, depends of clock frequency and read out mode

0,32,64,96 | 8,40,72,104 | 16,48,80,112 | 24,56,88,120 || 1,33,65,97 | 9,...

Vienna with 4 APV connected to a fan out

Trigger input Clock synchronized trigger TTM signals like clock, event number, … 4 anal signal Clock. trigger + HV Control sig. U/V Si det. Hybrid Second repeater Clock in Test system to readout U/V Si sensor Prototype for final system readout for the APV25 Test at KEK 6-9 april 2005 APVDAQ: Signals for repeater Crate bus control with TTM signals TDC for trig./clock time still missing Repeater with AC coupling Protection system against short current and base line restore - HV

Proposal for the ADC signal processor of the future Si. Vertex Detector for BELLE for the APV25 Si. Read out Ic Every input has its own data processor. The experience of the RAL CMS group (Tracker-FED) will be utilized to design the APV25 signal processor (pedestal subtraction, CMC, hit finding,…). How far we want to go in hardware data processing on the module is open. Anyhow it is foreseen to switch between three different modes: - Full (transparent) APV25 data - the data above a threshold with coordinates - hit data with peak time information For test purposes, we could store information of all 3 modes.

Fast event data block output, up to 80 MHz, 32 or 64 bit The module would be very similar to that for the CMS pixel readout system and can be ready in short time. Event rate up 100kHz could be possible. Depends on the number of time slices and clock frequency. Serial hit data output from every input channel for a fast track trigger ADC clock: Clock phase can be adjusted for every input channel

The final CMS Pixel-FED Electrical input card instead of optical receiver Connectors for electrical Daughter card exist. We build an extra input daughter card, which use this connector Clock- control signal (same as that for FADCTF TTM system) TTC system for clock and trigger not needed Not used S-link output 64 Bit/ 80 MHz Was tested at Vienna and now tested at PSI,Switzerland

4 ADC Dau. 4 times 10 bit data clocks with adjustable phase Altera Daughter 9 inputs 9 data proc + FIFO’s P1P1 P2P2 64 (or 32 bit) bit data bus 40 MHz+4 control lines 9 lines with information for trigger proc. Fast data transfer to PCI protocol is open 32 or 64 bit P3P3 VME protocol Altera Altera daughter with final FIFO Schematics of the ADC with the possibility of single channel processing and output with data for trigger processor (module exists) Delayed clock and control sig. distributor, VME control Altera Transmit crate clock, control signals and event number from TTM system and a serial output for every input (36) Fast Control bus 32 Bit Address/data bus 36 Input9-RJ45 connectors36 Input9-RJ45 connectors Every output of a fast signal like data, clock or strobe is connected only to one input. Serial termination.

Event data block from all 36 inputs 64 bit or 32 bit data S-link or ??? Serial trigger data output from every input data stream like existing L1.5 trigger 9UVME9UVME Trigger proc. COPPER ? Trigger lines from some ADC modules buf fer Parallel hit data for trigger processor 12 bit data stream or Data Proc. COPPER ? ADCADC The fast data output could also include hit information for trigger ?

How could we reduce the occupancy of the Si. strip detector with little extra cost? One possibility would be to measure the time between trigger and the hits. Thus off-time hits can be discarded. Hits in the selected trigger window are event candidates. The APV25 has the possibility to store 3 consecutive samples (spaced by the system clock) of a signal (multi-peak mode) with one trigger. With a second trigger just 3 clocks later, you can get the next 3 time samples of the shaped input signal. We can use this possibility to determine the time between shaped detector signal and clock. We can also measure the time between the trigger signal and the clock for the APV25. (Trigger can come at any time w.r.t. the clock.) With those 2 timing values we can select if the hit belongs to the event or not. With 6 time slices we would also detect pile-up effects from additional signals before or after the signal of interest and in most cases we can also calculate the time. Occupancy reduction with the possibilties of APV25

Background reduction using the multi-peak mode Most hits from background events are not correlated (in time) with the trigger (continuous beam). At the moment we have a time window to accept data of >2400 ns for the VA1TA and ~150ns (50ns peaking time) for the APV25. This window of 150ns should be reduced again. We know both the peak time of the shaped signal and the time between incoming and clock synchronized trigger. We use this information to select the hits resulting in a much smaller time window. Additional reduction of the time window (and thus of the background) by a factor around 8-10! The effective time window, where a signal is accepted, could be around 20-15ns compared to >2400ns for the VA1TA without a strip length reduction (provided that we have a precisely timed trigger). A simple preselection could be programmed into the Altera chip. The data flow would be strongly reduced, because only data with belongs to the trigger in a reduced time window are transferred. No hardware modification needed.

The shaping time is adjustable for the APV25 Threshold Even a short peaking time (eg 50ns) creates a wide time window for background (~150ns)

12 time slices of a shaped input signal created by 4 triggers spaced by 3 clocks. For time calculation we can use 3 ore more pulse height values, depending on the shaping time

S1 S2 S3 shaping time like that, S1 s3 The time between the trigger information of the TOF, if exists (or other time references), and the clock synchronised trigger for the APV25 can be measured and transmitted to the FADC system. Assuming that the signal peaks in the desired time window, we can expect a certain relation between the samples S1, S2, S3 of the shaped signal. By using 6 samples, we could possibly detect and mostly correct pile-ups for S1, S2, and/or S3 from a signal before or after the wanted signal. Manfred Pernicka, Hephy, Vieanna

. S1 S2 S3 Trigger D Clo 40 MHz clock Q Time difference between 0 and 25 ns must be measured S1 S2 S3

Threshold above which every signal would be stored using a discriminator. Region where signals would be discarded, even though above threshold depends on the shaping time Effective time window Selection e.g.: S 1 <S 3 <S 2 Quick calculation Minimum condition: 3 consecutive time slices with signals above threshold That could be done on the ADC module

Between function and measured filter wave form nearly no difference

M. Friedl M.Pernicka, Hephy. Vienna M. C. signal with noise Accepted as signal above threshold Selected with S1,S3<S2Selected S1<S3<S2 and S3<S1<S2 ~230 ns <50ns ~25ns Threshold As signal detected time width ~230 ns

2400ns above threshold = accepted as signal 150 ns above threshold Reduction factor ~16 Reduction factor in compare VA1TA and APV25 VA1TA shaping time 800ns >2400ns APV shaping time 50ns >150 ns Using time information of signal and trigger to clock 150 ns ~15 – 20 ns Reduction factor ~10-8 Manfred Pernicka Hephy, Vienna (Reduction factor without factor for shorter Si strips) Final reduction ~ Cost: something Cost: nothing but requires the APV

Correlations between u- and v-coordinates For matching hits in u and v, the following data are correlated and can be used to create a fast trigger: 1)time of the hit 2)pulse height 3)cluster size These correlations can be used to remove ambiguities, eliminate ‘ghost hits’ and thus reduce background A requirement on the cluster size can be used to reject hits from tracks with don’t originate from vertex Some of these requirements could be programmed into the Altera firmware. However, one FPGA-Altera has to handle one sensor ( U and V with 16 APV25 )

same amplitude same time and cluster width

First Results p-side 51µmp-side 102µmn-side 51µmn-side 102µm Cluster signal [e] k / 19k Strip noise [e] Cluster SNR / 31 Cluster width Preliminary properties of the UV striplet sensor with double-sided APV25 readout, measured at the KEK beam test 6-9 April 2005: Compatible to single-sided measurements (CERN August 2004)

First Results – U/V correlations

First Results – U/V correlation quality Time U/V Ampl. U/V

Linear fits for scatter plots and calculation of errors (“residuals”) Residual plots and Gaussian RMS:  U/V amplitude: 1800 e  U/V cluster width: 0.4  U/V timing: 2.7 ns  TDC/U timing: 2.3 ns Good results: Amplitude and timing correlations can help a lot for hit finding (noise elimination and ghost reduction)!

Summary APV25 possibilities and his data read out system Apv25 designed for CMS and we can use a lot of experiences For future production of APV25 ? Hybrid, repeater and VME APV control system exist for test run Final system ADC Module exists, but programmed for CMS pixel, Must be programmed for BELLE APV25 purpose Processing power proved by pixel data processing Many processing steps at the same clock cycle, no dead time, only delay Occupancy reduction (Nominal) peaking time of the APV25: 50ns 3,6,9,.. time samples of a shaped APV25 signal possible (multi-peak mode) Additional reduction factor (compared to single sample readout of the APV25) around 10 Time correlation between U and V data helps for pattern recognition Beam Test 42 GB of data recorded within 3 days SNR~25 / 28 obtained for p / n-sides at standard conditions. U/V correlations: amplitude: RMS=1800 e, timing between U/V: RMS=2.7 ns

APVDAQ control module for APV25 readout TTM timing control could be used to transmit clock, trigger, address, L1.5 accept, … and to measure the time between incoming and APV25-synchronized trigger. TTM input Trigger input from TOF Sync. trigger out

Ready for BELLE: the complete event data transfer and the final data block building can be used from the Pixel system (32 bit data bus sufficient instead of 64). The APV25 data processor has to be programmed for BELLE.

25 ns ~8..ns Clock nClock n+1 Clock Trigger clock synchron Trigger 0 1,2 3 01/