Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 9 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Test Power Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 92 Power Considerations in Design A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function. A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function. Power buses are laid out to carry the maximum current necessary for the function. Power buses are laid out to carry the maximum current necessary for the function. Heat dissipation of package conforms to the average power consumption during the intended function. Heat dissipation of package conforms to the average power consumption during the intended function. Layout design and verification must account for “hot spots” and “voltage droop” – delay, coupling noise, weak signals. Layout design and verification must account for “hot spots” and “voltage droop” – delay, coupling noise, weak signals.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 93 Testing Differs from Functional Operation VLSI chip system System inputs System outputs Functional inputs Functional outputs Other chips

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 94 Basic Mode of Testing VLSI chip Test vectors: Pre-generated and stored in ATE DUT output for comparison with expected response stored in ATE Automatic Test Equipment (ATE): Control processor, vector memory, timing generators, power module, response comparator Power Clock Packaged or unpackaged device under test (DUT)

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 95 Functional Inputs vs. Test Vectors Functional inputs: Functional inputs: Functionally meaningful signals Functionally meaningful signals Generated by circuitry Generated by circuitry Restricted set of inputs Restricted set of inputs May have been optimized to reduce logic activity and power May have been optimized to reduce logic activity and power Test vectors: Test vectors: Functionally irrelevant signals Generated by software to test modeled faults Can be random or pseudorandom May be optimized to reduce test time; can have high logic activity May use testability logic for test application

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 96 An Example VLSI chip Binary to decimal converter 3-bit random vectors 8-bit 1-hot vectors VLSI chip system VLSI chip in system operation VLSI chip under test High activity 8-bit test vectors from ATE

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 97 Comb. Circuit Power Optimization Given a set of test vectors Given a set of test vectors Reorder vectors to minimize the number of transitions at primary inputs Reorder vectors to minimize the number of transitions at primary inputs Combinational circuit (tested by exhaustive vectors) Rearranged vector set produces 7 transitions transitions

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 98 Reducing Comb. Test Power V1V2V3 V4V Original tests: V1 V2 V3 V4 V5 10 input transitions Traveling salesperson problem (TSP) finds the shortest distance closed path (or cycle) to visit all nodes exactly once. But, we need an open loop solution. Reordered tests: V1 V3 V5 V4 V input transitions

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 99 Open-Loop TSP Add a node V0 at distance 0 from all other nodes. Add a node V0 at distance 0 from all other nodes. Solve TSP for the new graph. Solve TSP for the new graph. Delete V0 from the solution. Delete V0 from the solution. V1V2V3 V4V V

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 910 Traveling Salesperson Problem A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, 2006.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 911 Scan Testing Combinational logic Scan flip- flops Primary inputs Primary outputs Scan-in SI Scan-out SO Scan enable SE DFF mux SE SI D D D’ SO 1010

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 912 Example: State Machine S5 S1 S4 S2 S3 Reduced power state encoding S1 = 000 S2 = 011 S3 = 001 S4 = 010 S5 = 100 State transition Comb. State input changes/clock 000 → → → → → → Functional transitions Functional state transitions

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 913 Scan Testing of State Machine Combinational logic FF=0 FF=1 Primary inputs Primary outputs Scan-in 010 Scan-out 100 State transition Per clock state changes 100 → → → Scan transitions

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 914 Low Power Scan Flip-Flop DFF mux SE SI D DFF mux SE SI D SO D’ SO Scan FF cellLow power scan FF cell 1010

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 915 Built-In Self-Test (BIST) Linear feedback shift register (LFSR) Multiple input signature register (MISR) Circuit under test (CUT) Pseudo-random patterns Circuit responses BIST Controller Clock C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: Springer, 2002.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 916 Test Scheduling Example R1R2 M1 M2 R3R4 A datapath

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 917 BIST Configuration 1: Test Time LFSR1LFSR2 M1 M2 MISR1MISR2 Test time Test power T1: test for M1 T2: test for M2

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 918 BIST Configuration 2: Test Power R1LFSR2 M1 M2 MISR1MISR2 Test time Test power T1: test for M1 T2: test for M2

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 919 Testing of MCM and SOC Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR). Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR). Test resources (R1,...) and tests (T1,...) are identified for the system to be tested. Test resources (R1,...) and tests (T1,...) are identified for the system to be tested. Each test is characterized for test time, power dissipation and resources it requires. Each test is characterized for test time, power dissipation and resources it requires.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 920 Resource Allocation Graph T1T2T3T4T5T6 R2R1R3R4R5R6R7R8R9

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 921 Test Compatibility Graph (TCG) T1 (2, 100) T2 (1,10) T3 (1, 10) T4 (1, 5) T5 (2, 10) T6 (1, 100) Tests that form a clique can be performed concurrently. Power Test time Pmax = 4

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 922 Test Scheduling Algorithm Identify all possible cliques in TCG: Identify all possible cliques in TCG: C1 = {T1, T3, T5} C1 = {T1, T3, T5} C2 = {T1, T3, T4} C2 = {T1, T3, T4} C3 = {T1, T6} C3 = {T1, T6} C4 = {T2, T5} C4 = {T2, T5} C5 = {T2, T6} C5 = {T2, T6} Break up clique sets into power compatible sets (PCS), that satisfy the power constraint. Break up clique sets into power compatible sets (PCS), that satisfy the power constraint.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 923 Test Scheduling Algorithm... PCS (Pmax = 4), tests within a set are ordered for decreasing test length: PCS (Pmax = 4), tests within a set are ordered for decreasing test length: C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5) C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5) C2 = {T1, T3, T4} → (T1, T3, T4) C2 = {T1, T3, T4} → (T1, T3, T4) C3 = {T1, T6} → (T1, T6) C3 = {T1, T6} → (T1, T6) C4 = {T2, T5} → (T2, T5) C4 = {T2, T5} → (T2, T5) C5 = {T2, T6} → (T2, T6) C5 = {T2, T6} → (T2, T6) Greedy solution: Greedy solution: Expand PCS into subsets of decreasing test lengths. Each subset is an independent test session, consisting of tests that can be concurrently applied. Expand PCS into subsets of decreasing test lengths. Each subset is an independent test session, consisting of tests that can be concurrently applied. Select test sessions, starting from the shortest-time PCS, to cover all tests. Select test sessions, starting from the shortest-time PCS, to cover all tests. Remove redundant PCS from the selected sessions. Remove redundant PCS from the selected sessions.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 924 TS Algorithm: Cover Table Test sessionT1T2T3T4T5T6Length (T1, T3, T4)XXX100 (T1, T5)XX100 (T1, T6)XX100 (T2, T6)*XX100 (T3, T5)XX10 (T2, T5)XX10 (T3, T4)XX10 (T5)*X10 (T4)*X5 Dropped as redundant sessions. Selected sessions are (T3,T4), (T2, T5) and (T1, T6). Test time = 120.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 925 An ILP Solution to Cover Problem Test sessionInteger 0,1 variableT1T2T3T4T5T6Length (T1, T3, T4)S1XXX100 (T1, T5)S2XX100 (T1, T6)S3XX100 (T2, T6)S4XX100 (T3, T5)S5XX10 (T2, T5)S6XX10 (T3, T4)S7XX10 (T5)S8X10 (T4)S9X5 Constraints:S1+S2+S3 ≥ 1implies T1 is covered S4+S6 ≥ 1implies T2 is covered similar constraints to cover T3, T4, T5 and T6

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 926 An ILP Solution (Cont.) Test sessionSi: Integer 0,1 variableT1T2T3T4T5T6Length, Li (T1, T3, T4)S1XXX100 (T1, T5)S2XX100 (T1, T6)S3XX100 (T2, T6)S4XX100 (T3, T5)S5XX10 (T2, T5)S6XX10 (T3, T4)S7XX10 (T5)S8X10 (T4)S9X5 9 Minimize ∑ (Li × Si)ILP solution:S3=S6=S7 = 1 i=1S1=S2=S4=S5=S8=S9 = 0 Test length = 120

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 927 A System Example: ASIC Z* RAM 2 Time=61 Power=241 RAM 3 Time=38 Power=213 ROM 1 Time=102 Power=279 ROM 2 Time=102 Power=279 RAM 1 Time=69 Power=282 RAM 4 Time=23 Power=96 Reg. file Time = 10 Power=95 Random logic 1, time=134, power=295 Random logic 2, time=160, power=352 *Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,” Proc. VLSI Test Symp., April 1993, pp. 4-9.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 928 Test Scheduling for ASIC Z Power Power limit = Test time 331 RAM 1 RAM 3 Random logic 2 Random logic 1 ROM 2 ROM 1 RAM 2 Reg. file RAM 4 R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI Systems under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp , June 1997.

Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 929 References N. Nicolici and B. M. Al-Hashimi, Power- Constrained Testing of VLSI Circuits, Boston: Springer, N. Nicolici and B. M. Al-Hashimi, Power- Constrained Testing of VLSI Circuits, Boston: Springer, E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer 2005.