Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1 Intel IXP1200 Network Processor q Lab 12, Introduction to the Intel IXA q Jonathan Gunner, Sruti Gorappa, Kerry Wood q Shiv Kalyanaraman q Yong Xia (TA) q q

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 2 First: What’s a Network Processor q Router vendors have built speed into their devices by pushing functionality down into hardware (ASICs). q ASIC: Application Specific Integrated Circuits q They’re fast, but they’re custom-made for each application and expensive to build. q Time to market for new implementations is extremely long, since algorithms must be implemented at the transistor/gate level. Network processors look to avoid these pitfalls by introducing specialized, software controlled devices that can be customized quickly. But they also process packets at near-wire speeds!

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 3 Intel Internet Exchange Architecture q Microengine technology — a subsystem of programmable, multi-threaded RISC microengines that enable high-performance packet processing in the data plane through Intel® Hyper Task Chaining. This multi- processing technology features software pipelining and low-latency sequence management hardware. q The Intel IXA Portability Framework — an easy-to-use modular programming framework providing the advantages of software investment protection and faster time-to-market through code portability and reuse between network processor-based projects, in addition to future generations of Intel IXA network processors. q Intel® XScale™ technology — providing the highest performance-to- power ratio in the industry.

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 4 Intel’s Gear (1) q IXP2850 q Designed for use in virtual private networks, secure web services, and storage area networks. q IXP2800 q Able to handle line rates ranging from OC-48 to OC-192. q IXP2400 q Designed for OC-12 to OC-48 network access and edge applications.

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 5 Intel’s Gear (2) q The IXP 1200 product line represents Intel’s first attempt in the area (it was actually inherited when they purchased Digital) q The IXP 1200 is a single-board chip, designed with abstractions in mind. q Since this is a new area, and it’s designed to be used with many different types of hardware and software, the documentation is incomplete/unavailable/or just plain wrong. q To achieve wire-fast speeds with software, the goal is to hide latency with parallelism. Processing packets is inherently parallel, and necessary for fast applications.

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 6 How does the IXP 1200 simplify the ASIC based design ? q A Typical ASIC Based Design q A processor to handle routing information and higher level processing q ASICs to handle each packet q An IXP 1200 Design q StrongArm Core to handle routing algorithms and higher level processing q Microengines to handle packet processing

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 7 Conceptually: Two Levels The IXP1200 is designed to process packets at wire speed, but also to handle control-plane information. 1. Strong ARM Core (1): q Designed to handle control-plane and slow-path processing. q Update host tables, forwarding tables, filtering, running routing protocols. q Runs an OS from a wide variety of sources (Linux derivatives / VxWorks). q Has limited access to certain resources on board. q Development is done using q WindRiver’s Tornado q Embedded Linux q ARM Software development kit q C/C++

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 8 Conceptually: Two Levels.. 2. Micro Engines (6): q Data-plane and fast-path processing. q Run no OS. Our model has a 2K instruction-store per microengine. q Multithreaded, 4 threads per engine. q Has access to all resources on board. Since there is no OS, and these are virtually unrestricted, we must carefully avoid thread traps! q Microengine Development Tools q Can write “microcode” or uEngine C q Microcode Assembler q Workbench q Write symbolic microcode q Assemble and optimize q Transactor q Debug and Simulation Engine

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 9 Misc. IX Bus: q Provides interface to network ports, hardware shortcuts (like hardware hash unit), super-fast and super-small scratch memory area. q StrongARM access to this is limited. It forces you to use the microEngines when you really don’t want to. Interface Devices q Intel does not specify a type of interface to be used. These could be ATM, Ethernet, FastE, GigE, wireless, etc.

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 10 IXP 1200 Building Blocks q SRAM q Store packet headers q SDRAM q Store packet data q PCI Interface q For accessing the control processor q Microengines and StrongArm Core make requests to SRAM and SDRAM. The IX Bus and PCI Bus also make requests to SDRAM. q Different type of queues for arbitration. Programmers can choose the queues depending upon their requirements.

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 11 Packet Flow Diagram

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 12 Design Solutions q Enterprise Routers q Streaming Video Server q Manipulation of digitized video. q Media Gateway q Seamless transport of voice from circuit- switched to packet-switched networks

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 13 Enterprise Router Line Card

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute Port Store and Forward Design q Receive Threads (16) q Receive packet from MAC port q Verify IP Header q Perform IP forwarding q Place packet on transmit queue q Transmit Scheduler Threads (2) q One per Microengine q Determine which transmit queue has packets q Assign work to each of three transmit threads q Transmit Threads (6) q Three per microengine q Send packet data to MAC port

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 15 Rx: Lookup and Queuing q Lookup the forwarding information in SRAM based on header fields q Read the forwarding information from SDRAM q Modify the header and writes it to buffer in SDRAM q Write packet descriptor to SRAM q Lock Transmit Queue in SRAM q Enqueue packet onto the corresponding Transmit Queue in SRAM q Set Port With Packets bit in scratch indicating that port has packets q Unlock Transmit Queue in SRAM

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 16 Tx q Transmit Scheduler q Sequentially checks each port for data by reading “Ports With Packets” in scratch memory. q Issues transmit assignments to the transmit threads. q Transmit threads. q Lock the transmit queue, dequeue packet, unlock queue. q Move packet from SDRAM to TFIFO and set TFIFO control bit.

Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 17 For more info…. q Jonathan Gunner q Slide Contributions from Kerry Wood and Shruti Gorappa