Calc2 Design Allows up to 4 incomplete requests on each port Tag is required to match request to response

Calc2 Typical Timing

Some Calc2 Test Cases

Test Generation Strategies 1.Deterministic vs. random - how tests are generated 2.Pregenerated vs. on-the-fly - when tests are generated

Generic Test Generation Algorithm Describe test generation possibilities as an algorithm The algorithm will be coded in HVL Decision points are key

Test Generation Alg. for Calc2 Port Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS

Deterministic, Pregenerated for Calc2 Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS Each path through the test gen. Algorithm flow is a test case Manually select a set of paths in the algorithm, prior to testing  May restrict paths to match test case requirements Manually generate expected responses

Deterministic, On-the-Fly for Calc2 Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS Manually specify important inputs deterministically Allow non-important inputs to be filled in randomly during simulation Must also specify interesting outputs

Deterministic, On-the-Fly for Calc2 Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS Stimulus generation must be intelligent - force overflow/underflow - Assign tags to avoid conflicts

Role of the Scoreboard Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS Port Number Tag Contains information on current transactions - tags, command, inputs, port - used by checker

Pregenerated Random Test Cases Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS Port Number Tag Test cases are not written manually, they are written in a directed random way Engineer provides a template for the test cases and some randomization parameters

Test Case Templates Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS Port Number Tag

Randomization Parameters Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS Port Number Tag Production rules are weighted to direct test stimulus generation

Result Checking Capture TAG Operand1 And CMD Set SHIFT_CMD_ LAST_CYCLE ON CLEAR ALL BUFFE RS AND QS Port Number Tag Golden Vectors Output vectors are stored in the scoreboard Checker compares DUV results to scoreboard data Cycle-Accurate Reference Model Reference model reimplements DUV function Checker compares reference model results to DUV outputs Transaction Based Testbench in defined in terms of “transactions” Scoreboard acts as a reference model, not cycle accurate

On-the-Fly vs. End-of-Test Checking On-the-Fly Easy to do using verification languages (assertions, etc.) Debugging is easier, access to entire state Lower memory requirements Probably increases simulation time End-of-Test Helpful if signal access is limited May be performed outside of simulation engine

Assertion-Based Result Checking Assertions act as a substitute for a complete reference model Example: Adder Assertions 1.If the LSBs of the inputs are the same then the LSB of the output is 0. 2.If the sign bits of the inputs are the same then the sign bit of the output is equal to the input sign bits (no overflow) Assertions catch some errors but not all errors

Debugging Bugs can exist in the following places: 1.Design 2.Environment (testbench) 3.Specification 4.Tools Tool bugs are less likely

Debug Process

Interactive Debugging Information Print Statements May be verbose May attach to monitors Assertions Efficient but may be incomplete Waveform Viewers Very verbose but shows timing information Memory Debuggers Dump entire state periodically Verbose but may reveal memory leaks