E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Wed, Nov 19 ExtractedRC simulation More Layout Secure Electronic Voting Terminal

Data Bus Machine Init FSM User ID FSM Selectio n FSM Confirm ation FSM Display User ID SRAM Message ROM Card Reader Fingerprint Scanner Encryption Key SRAM User Input Write-in SRAM Choice SRAM TX_Check Selection Counter Key Register XOR 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder XOR 8 bit MUX bit Add/Sub 01 8 bit MUX 16bi t REG 8-bit REG COMMS Register Shift Registe r In Shift Registe r Out constant init

COMMS Extracted RC Simulations functioning Buffering added to fix glitches

Unbuffered Simulation

Buffered Simulation

FSM Extraceted RC simulations work 33% of the layout still needs to be cleaned up

FSM Layout

MI FSM

UI FSM

Whole FSM

SRAM Row decoders: Complete and LVSing SRAM layout: Complete and LVSing ExtractedRC Simulation In Progress Next time: More Simulation for ExtractedRC

2bit_Dec+SRAM Write ExtratedRC

3bit_Dec+SRAM Write ExtratedRC

SRAM Plus 6 bit Decoder with Tristate Buffers Area: by Transistor: 3628 Density: 0.603

Entire Layout

TODO: Merge Our Cadence Directories Finish Layout cleanup Layout: User Input, Key Register, Message ROM Global Inter connects Simulations