Implementation of neuronetwork system on FPGA (characterization presentation) supervisor: Karina Odinaev Vyacheslav Yushin Igor Derzhavets Winter 2007

Project definition. 1.Goal: create FPGA based system for string/pattern matching with high code optimization for FPGA structure. 2.The system will have 3 main hardware elements: a.XUPV2P FPGA board. XUPV2P b.DLP-USB245M USB Adapter c.PC with USB port.

Data Flow Definition 1.Running special API with testing file as one of the arguments. a. The structure of input file is strings of different length. 2.API will inject the string to the FPGA through the USB adapter. 3.FPGA will process the data and update the status bit according to processing result. 4. Status bit from FPGA will be transferred through the USB adapter to API. 5.API will write the status to the output file

Data Flow Definition (cont.)

FPGA processing.  FPGA programmed according previous project with small tunings of result calculation, allowed by modular design.  FPGA will be synchronized with input device (no dummy clocks allowed).

Neuron network processing way.  The algorithm of networks processing based on the CLA (constructive learning algorithm)  Reference: pdf?arnumber= and pdf?arnumber= pdf?arnumber=374191

Timelines  27/11/06 - VHDL code ready.  1/12/06 - Finish API code writing.  5/12/06 - synthesize the whole project and debug the API -> FPGA input interface.  10/12/06 – finish debug whole project.  15/12/06 – make placement optimization (if possible) and run full benchmark for performance validation.

Input file data Board: USB adapter