OpenSPARC Program – Updates Thomas Thatcher OpenSPARC Engineering RAMP Retreat – January 2009, Berkeley

RAMP Retreat-Jan Agenda Quick OpenSPARC Overview > Current T1 Release Progress timeline Current Status > OpenSPARC University Program > OpenSPARC FPGA Board > Ubuntu Linux Boot > Multi-core T1 design: Progress Update Roadmap Q & A

RAMP Retreat-Jan What is OpenSPARC? Open-Sourced versions of Sun's Microprocessor Products > RTL, Verification Env,documentation, system software > Available for download at Two Processors Available > OpenSPARC T1 > 8 cores, 4 hardware threads per core > 1 floating-point unit external to core, shared by all cores > 4 banks of L2 cache > OpenSPARC T2 > 8 cores, 8 hardware threads per core > Floating-point internal to core, one per core > 8 banks of L2 cache

RAMP Retreat-Jan OpenSPARC Contribution Full 64-bit multi-thread SPARC Cores > Ability to choose number of threads, cores > Implementation on Xilinx FPGAs > Multi-core, coherent memory, with Xilinx peripherals Uniform software stack > Hypervisor abstraction layer > Choice between OpenSolaris or Linux operating systems Full Verification, synthesis, and system environments > Enables experimentation and research

RAMP Retreat-Jan OpenSPARC T1 SPARC V9 implementation Eight cores, four threads each – 32 simultaneous threads All cores connect through a GB/s crossbar switch High BW 12-way associative 3 MB on-chip L2 cache 4 DDR2 channels (23 GB/s) ‏ 70W power ~300M transistors

RAMP Retreat-Jan OpenSPARC T1 1.6 Release Released May, 2008 Implementation of 4-thread T1 core on Virtex 5 FPGAs > ML505-V5LX110T board > EDK Project files (for EDK 9.2) ‏ > Scripts to run complete RTL regression on hardware Complete setup to boot OpenSolaris > Networking support, including telnet and ftp Quick start ace files included > Creates an out-of-the-box experience > T1 core boots OpenSolaris in 30 minutes

RAMP Retreat-Jan Sun/Xilinx Partnership: Big Goals Proliferation of OpenSPARC technology Proliferation of Xilinx FPGA technology Make OpenSPARC FPGA friendly > Create reference design with complete system functionality > Boot Solaris/Linux on the reference design > Open it up > Seed ideas in the community Enable multi-core research

RAMP Retreat-Jan Timeline July 06 Jan 07 June 07 Jan 08 Aug 08 Jan 09 Sun/Xilinx OpenSpARC Stand-alone OpenSolaris on Ubuntu Linux Collaboration T1 on ML411 program under ML411 board Boot Begins board hypervisor First ML505 SupportDual-core boot OpenSPARC T1 Today

RAMP Retreat-Jan Hardware Block Diagram SPARC T1 Core processor-cache interface (PCX) ‏ Microblaze Proc Fast Simplex Links interface (FSL) ‏ CCX-FSL Interface External DDR2 Dimm MPMC MemCon Microblaze Debug UART IBM Coreconnect XPS Bus SPARC T1 UART 10/100 Ethernet MultiPort Memory Controller FPGA Boundary Xilinx Embedded Developer’s (EDK) Design Developed and Working Cache-processor interface (CPX) ‏

RAMP Retreat-Jan Status: OpenSPARC University Program World-wide acceptance of OpenSPARC by universities for curriculum or research purposes Sun and Europractice sign 3-year agreement > Will collaborate to promote OpenSPARC as a reference design to over 500 universities in Europe New slide-cast training available > 12 modules of on-line training > Recorded voice with slide display > Equivalent to a 2-day OpenSPARC workshop

RAMP Retreat-Jan OpenSPARC Internals Book Covers both OpenSPARC T1 and T2 Includes > Architectural Overview > Development environments for OpenSPARC > Source (RTL) code overview > Configuring, extending, and verifying OpenSPARC > Porting operating systems to OpenSPARC 350 Pages Available in both hardcopy (Amazon.com) and PDF format ‏

RAMP Retreat-Jan OpenSPARC Development Kit A kit for OpenSPARC development > Board based on the ML505, but with an XC5VLX110T FPGA > Includes USB interface for FPGA programming > Tested with OpenSPARC T1 release 1.6 release design > Eliminates the need to buy a board and then upgrade the FPGA Began shipping in August Kit Includes: > Board, with power supply and 256 MB DRAM > Platform USB download cable > Host to host SATA crossover cable > Compact flash card with OpenSPARC T1 1.6 ace files

RAMP Retreat-Jan Kit Contents

RAMP Retreat-Jan OpenSPARC Kit Donation Program Sun will donate OpenSPARC Development Kits to qualified universities > Web address below: > Over 100 donated so far > Still not too late to apply! > See the web page for more details Also available from directly from Digilent >

RAMP Retreat-Jan OpenSPARC in GRLIB Gaisler Research announces the integration of the OpenSPARC T1 core in GRLIB distribution > Allows AMBA-based T1 systems > Enables broad portfolio of peripherals for OpenSPARC > Appears in release grlib-gpl b3188 > Supports 3 FPGA boards It just got a LOT easier to use OpenSPARC in your designs!

RAMP Retreat-Jan Ubuntu Linux Boot We successfully booted Linux on a 4-thread FPGA implementation of the T1 core. > Standard installation > Console change for polled I/O > Needed to add RAM disk driver > RAM disk size is 80MB > Boots full version in about an hour

RAMP Retreat-Jan Multi-core system on FPGA Boards We have created a multi-core system by interconnecting two boards. > Opens the door to multi-core designs on BEE3 board Uses Xilinx Aurora link-layer protocol running over RocketIO™ GTP serial tranceivers > Connected through the SATA connectors on the board Each GTP channel is 16 bits at 75 Mhz > Connected to Microblaze through an FSL FIFO

RAMP Retreat-Jan Multi-core System Block Diagram SPARC T1 Core Microblaze Proc Fast Simplex Links (FSL) ‏ CCX-FSL Interface External DDR2 Dimm MemCon Microblaze Debug UART SPARC T1 UART Ethernet Xilinx CacheLink (XCL) ‏ FPGA Boundary Xilinx Embedded Developer’s (EDK) Design Developed and Working New Aurora over GTP FSL connected Aurora-over-GTP module to connect to other board

RAMP Retreat-Jan Dual-core system implementation SATA Cable Master Node

RAMP Retreat-Jan Four-core system implementation SATA Cable SMA cables Master Node

RAMP Retreat-Jan System Configuration Master FPGA hosts entire OpenSPARC Address space. > However, Each client MicroBlaze will run firmware code out of its own memory Both boards have the same bit file > Avoids need to develop and implement separate bit files > CPU ID set by DIP switches on the board However, software will be different for each board > Master software: services all memory requests > Slave software: only routes memory requests to the other board

RAMP Retreat-Jan Dual-core design Progress In August, a dual-core system had booted to Hypervisor Have been working through various issues with the dual- core design System now boots to Solaris login prompt. > Still some issues. We are working through them BeeCube is also working on a multi-core design for the BEE3 board

RAMP Retreat-Jan Roadmap OpenSPARC T1 release 1.7 > Setup to boot Ubuntu Linux > Update of EDK project to EDK 10.1 > Improvements to memory controller > Improvements to place and route > Multi-core design Future Work > Clear the remaining obstacles to getting Solaris running on a multi-core design

RAMP Retreat-Jan Summary OpenSPARC: The tools you need to do multi-core research! > Complete EDK project to implement a system > Implemented on both BEE3 board and OpenSPARC Kit > Complete verification environment > Complete software stack > OpenSolaris Boot demonstrated > Ubuntu Linux boot demonstrated > Training materials available

RAMP Retreat-Jan Innovation will happen everywhere OpenSPARC momentum Innovation Happens Everywhere > downloads