NuCAD ELECTRICAL ENGINEERING AND COMPUTER SCIENCE McCormick Northwestern University Robert R. McCormick School of Engineering and Applied Science Nostra-XTalk : A Predictive Framework for Accurate Static Timing Analysis in UDSM VLSI Circuits Debasish Das, Ahmed Shebaita Yehea Ismail, Hai Zhou EECS, Northwestern Kip Killpack Strategic CAD Lab, Intel

June 26, 2015 (2) Outline Motivation and Previous Research Directed Search Mechanism Static Timer Algorithm Experimental Setup Conclusions and future work

June 26, 2015 (3) Coupling Dominates Coupling cap dominates interconnect parasitics Graph shows ratio of coupling cap vs. ground cap of nets  Parasitics extracted from 65 nm logic block  Industrial Microprocessor design from Intel

June 26, 2015 (4) Previous Research (Coupling Model) Accurate computation of MCF needed  To model the effects of crosstalk Analytical models for MCF computation proposed  Step transitions : (0,2) Sapatnekar et.al, ICCAD 2000  Ramp Models : (-1,3) Kahng et.al, DAC 2000 Chen et.al, ICCAD 2000  Exponential Models : (-1.885,3.885) Ghoneima et.al, ISCAS 2005 Accurate models are applied to timing analysis  Extending Ramp model to Timing Analysis Das et. al, ICCD 2006

June 26, 2015 (5) Previous Research (Timing Analysis) Timing Analysis with coupling iterative Iterative analysis with continuous models: Chen et.al ICCAD 2000 Iterative analysis with discrete models: Sapatnekar et.al TCAD 2000, Chen et.al ICCAD 2000, Arunachalam et.al DAC 2000 Circuit and coupling structure explored to speed up iterative analysis: Das et. al ICCD 2006

June 26, 2015 (6) Issues in Previous Research Analytical models derived MCF based on  Output delay windows on victim and aggressor nets  Output slew windows on victim and aggressor nets Correlation between input timing windows and MCF ignored Correlation between input slew windows and MCF ignored Such assumptions may lead to pessimistic MCF computation

June 26, 2015 (7) Motivational Example Rise Delay Window at I1  [2,4] Fall Delay Window at I2  [3.5,4.5] Static timing assumption on slews  Max victim input slew 0.6  Min aggressor input slew 0.8 Consider 2 timing events from [2,4] (arrival time, slew)  T1 = (3.9,0.6)  T2 = (4.0,0.6) G1 G2 I1 I2 O1 O2 [2,4] [3.5,4.5]

June 26, 2015 (8) Motivational Example MCF due to T1 = 2.5 MCF due to T2 = 2.4 Previous approaches will consider MCF as 2.5  Update [2,4] with MCF 2.5 Ideally  Compute Delay push-out on T1 due to MCF 2.5: T1 po  Compute Delay push-out on T2 due to MCF 2.4: T2 po  Maximum bound of output window max(T1 po,T2 po ) G1 G2 I1 I2 O1 O2 [2,4] [3.5,4.5]

June 26, 2015 (9) Salient Features  Directed Search Mechanism Search for input timing event  Results in worst/best delay push-out  Use of input timing windows on victim and aggressor Accurate gate delay model employed  To take into account non-linearity of devices  Iterative static timer Using Directed Search on a victim cluster  Collection of all aggressor nets connected to victim net

June 26, 2015 (10) Outline Motivation and Previous Research Directed Search Approach Static Timer Algorithm Experimental Setup Conclusions and future work

June 26, 2015 (11) Circuit Model Rise/Fall-Delay-Window : (Di l, Di h ) Rise/Fall-Slew-Window : (si l,si h ) Associated nodes with coupling edge : N1 and N2 NAND CC N1 N2 N3 CC N1 NAND I1 I2 Rise Arc Fall Arc Coupling Edge

June 26, 2015 (12) Circuit Model for Directed Search Enumerate arcs on drivers  Both victim and aggressor net N1 arc1 arc2 N2 arc3 arc4 c Input delay (ID a ) =[Di a l, Di a h ] Input slew (ID a )=[si a l, si a h ] Aggressor Input delay (ID v )=[Di v l, Di v h ] Input slew (IS v )=[si v l, si v h ] output delay (OD v ) D 0 v =[Do v l, Do v h ] output slew (OS v ) t v s =[so v l, so v h ] output delay (OD a ), D 0 a =[Do a l, Do a h ] output slew (OD a ), t a s =[so a l, so a h ] arc1 ID v,IS v ID a,IS a arc3 Victim c arc2 ID v,IS v ID a,IS a arc3 c arc1 ID v,IS v ID a,IS a arc3 c arc2 ID v,IS v ID a,IS a arc4 VictimAggressor OD v,OS v OD a,OS a OD v,OS v OD a,OS a OD v,OS v OD a,OS a OD v,OS v OD a,OS a

June 26, 2015 (13) Circuit Model for Directed Search (contd.) Enumerate arcs on drivers  Both victim and aggressor net N1 arc1 arc2 N2 arc3 arc4 Aggressor Victim Apply Directed Search on 4 possibilities  Choose the one that results in worst delay push-out c ID v,IS v ID a,IS a arc3 c ID v,IS v ID a,IS a arc3 c arc1 ID v,IS v ID a,IS a arc3 c arc2 ID v,IS v ID a,IS a arc4 OD v,OS v OD a,OS a OD v,OS v OD a,OS a OD v,OS v arc1arc2

June 26, 2015 (14) Detailed Circuit Model for Directed Search Input delay (ID a ) =[Di a l, Di a h ] Input slew (ID a )=[si a l, si a h ] Input delay (ID v )=[Di v l, Di v h ] Input slew (IS v )=[si v l, si v h ] output delay (OD v ) D 0 v =[Do v l, Do v h ] output slew (OS v ) t v s =[so v l, so v h ] output delay (OD a ), D 0 a =[Do a l, Do a h ] output slew (OD a ), t a s =[so a l, so a h ] Victim Aggressor Coupled CircuitEquivalent Circuit c arc1 ID v,IS v ID a,IS a arc3 OD v,OS v OD a,OS a C v = C g + (Victim MCF)C c arc1 ID v,IS v ID a,IS a arc3 OD v,OS v OD a,OS a C a = C g + (Aggressor MCF)C c

June 26, 2015 (15) Gate Delay Model We use logic gates from Faraday’s 90 nm cell libraries  Figure (a) shows t v s = f1(C v,si v )  Figure (b) shows t a s = f2(C a,si a )  Figure (c) shows t v d = f3(C v, si v )  Figure (d) shows t a d = f4(C a, si a ) Assuming linear dependance is acceptable Output Waveform on victim  W v = G(D i v + t v d, t v s ) Output Waveform on aggressor  W a = G(D i a + t a d, t a s ) si v h si v l cvcv tvdtvd si v h si v l cvcv tvstvs si a h si a l tadtad si a h si a l caca tastas caca (a) (b) (c) (d)

June 26, 2015 (16) Coupling Model (Das et. al, ICCD 2006) Overlap ratio (k) computation  Overlap ratio is defined as the ratio of aggressor output waveform that overlap with victim threshold voltage Use waveforms W v and W a to compute k

June 26, 2015 (17) Coupling Model (Das et. al, ICCD 2006) Use waveforms W v and W a to compute k (a) Victim MCF = 1±2k, Aggressor MCF = (b) Victim MCF = 1±2k, Aggressor MCF = (c) Victim MCF = 1±2k, Aggressor MCF = (d) Victim MCF = 1±2k, Aggressor MCF =

June 26, 2015 (18) Worst Case Delay Computation Linearly span the domain of k Victim capacitance C v = C g + (1+2k)C c  Compute t v d and t v s Aggressor capacitance and slew are given by si v h si v l cvcv tvstvs si v h si v l cvcv tvdtvd c g +(1+2k)c c

June 26, 2015 (19) Worst Case Delay Computation (contd.) Using t a s we obtain aggressor capacitance [c1,c2] t a d is calculated using c1 and c2 caca si a h si a l tastas si a h si a l caca tadtad c 1 c 2 Worst case delay computation produces Construct Feasible set F Choose one element from F which has worst t v d

June 26, 2015 (20) Outline Motivation and Previous Research Directed Search Approach Static Timer Algorithm Experimental Setup Conclusions and future work

June 26, 2015 (21) Practical Application of Directed Search Victim net coupled with more than one aggressors We model our circuit as directed graph G = (V,E)  V : Gates in combinational circuit  E : F U C where F : Fan-out Edges C : Coupling Edges We give the following definition V is the victim node while A i are its aggressors

June 26, 2015 (22) Worst Case Coupling Capacitance as fix- points We define a switching point as an ordered pair of delay and slew Following set gives all possible switching points in a k-cluster Set formed by pairs of switching points (s i,s j ) is a totally ordered set Directed Search between an victim and aggressor is order preserving transformation Fix-point iteration to get worst case caps

June 26, 2015 (23) Iterative Static Timer Algorithm

June 26, 2015 (24) Outline Motivation and Previous Research Directed Search Approach Static Timer Algorithm Experimental Setup Conclusions and future work

June 26, 2015 (25) Circuit Modeling Experiments done on ISCAS85 benchmarks Circuit modeled as DAG (Timing Graph) Nodes in Timing Graph are Gates Edges represent interconnect Nodes are mapped to ASIC logic gates  Faraday 90 nm experimental tech library used  Delay tables are used : f( output load, input slew ) Coupling graph generation  Extracted coupling capacitance values are used  Coupling graph is superimposed on timing graph  Each net is assumed to couple with 6 aggressors

June 26, 2015 (26) Accuracy Enhancement Results IST-(0,1,2) : Iterative static timer MCFs 0,1,2 (Sapatnekar et. al) IST-DS : Proposed Iterative static timer RT : Runtime TA : Cell Table Accesses GA : Accuracy Gain, GT : Gain in Cell Table Accesses

June 26, 2015 (27) Accuracy Enhancement Results Hold time given by IST-(0,1,2) can be non-conservative Accuracy Gain by proposed algorithm  Average : 25.59%  Highest gain C880 : 45.5% Decrease in Cell Delay Table Lookup by proposed algorithm  Average : 40.1%  Maximum decrease c6288 : 64.8% Decrease in cell delay is not reflected in runtime  Search has high complexity  Search should be used judiciously

June 26, 2015 (28) Outline Motivation and Previous Research Directed Search Approach Static Timer Algorithm Experimental Setup Conclusions and future work

June 26, 2015 (29) Conclusions and future work We present Nostra-XTalk  Directed Search Approach for accurate timing analysis  Iterative static timer using directed search Directed Search is time consuming Directed Search should be selectively applied Can be used in a coupling partitioning based timer  As proposed by Das et. al ICCD 2006  Directed Search can be applied on local clusters Future Directions  Devise algorithms Selectively apply Directed Search Accurate as well as efficient analysis