Altera’s Quartus II Installation, usage and tutorials Gopi Tummala Lab/Office Hours : Friday 2:00 PM to 4:00 PM at EBU3B 3219

Outline  Altera Quartus II Download  Installation  Starting Quartus II  Usage Tutorials  Verilog two-way light controller circuit example  Typical CAD Flow  Getting Started  Starting a New Project  Verilog Design Entry  Compiling the Design  Pin Assignment  Simulating the Designed Circuit  Links

Download Quartus II Software  Go to ii/web-edition/qts-we-index.html ii/web-edition/qts-we-index.html  This is the webpage for the Quartus II software from Altera. Feel free to read through some of the links to get better acclimated with the program and what it offers  Click on the download link, and download the Quartus II Web Edition (v10) software for Windows.  You need to fill out a form and register at Altera  Note, you might as well make an account with them, as this helps when you are applying for the Quartus II license (not for the web version)  This is 2.9GB file. Check your bandwidth before you download and ensure you do not break the download (or) use smart downloading accelerators

Install Quartus II Software  Install Quartus II software.  Go through the installation procedure and install the complete program.  This takes a while so feel free to surf the web or refer to links at the end of this presentation

Starting Quartus II  To start the Quartus II software, follow these steps:  On the Windows Start menu, point to Programs, point to Altera, point to Quartus II, and then point to Quartus II (32-bit) or Quartus II (64-bit).  (web edition doesn’t have a 64-bit version)

Running the program and Tuts  Run the program. When it prompts you for Look & Feel, choose Quartus II. You should then see a pop up screen asking you to create a new project, or open interactive tuturial. Feel free to check out the tutorial. You can close that screen too.

Typical CAD Flow The CAD flow involves the following steps:  Design Entry – the desired circuit is specified either by means of a schematic diagram, or by using a hardware description language, such as Verilog or VHDL  Synthesis – the entered design is synthesized into a circuit that consists of the logic elements (LEs) provided in the FPGA chip  Functional Simulation – the synthesized circuit is tested to verify its functional correctness; this simulation does not take into account any timing issues

Typical CAD Flow  Fitting – the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip; it also chooses routing wires in the chip to make the required connections between specific LEs  Timing Analysis – propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit  Timing Simulation – the fitted circuit is tested to verify both its functional correctness and timing

Typical CAD Flow  Programming and Configuration – the designed circuit is implemented in a physical FPGA chip by programming the configuration switches that configure the LEs and establish the required wiring connections

Quartus II Tutorial using Verilog example  Creating a project  Design entry using Verilog code  Synthesizing a circuit specified in Verilog code  Fitting a synthesized circuit into an Altera FPGA  Assigning the circuit inputs and outputs to specific pins on the FPGA Chapters 1-5 in the attached tutorial

Simulation using Modelsim 6.5e Creating the Working Library: In ModelSim, all designs are compiled into a library. You typically start a new simulation in ModelSim by creating a working library called "work," which is the default library name used by the compiler as the default destination for compiled design units. Compiling Your Design: After creating the working library, you compile your design units into it. The ModelSim library format is compatible across all supported platforms. You can simulate your design on any platform without having to recompile your design. Loading the Simulator with Your Design and Running the Simulation: With the design compiled, you load the simulator with your design by invoking the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). Assuming the design loads successfully, the simulation time is set to zero, and you enter a run command to begin simulation. Debugging Your Results: If you don’t get the results you expect, you can use ModelSim’s robust debugging environment to track down the cause of the problem.

Simulation using Modelsim 6.5e - Tutorial  Ch 1 & 3 in Tutorial : Ch 1, 2, 7 and 9 in user manual

Link to download Quartus Altera Quartus II links and Tutorial Links  edition/qts-we-index.html edition/qts-we-index.html    ftp://ftp.altera.com/up/pub/Altera_Material/QII_9.0/Digital_Logic /DE1/Tutorials/Verilog/ ftp://ftp.altera.com/up/pub/Altera_Material/QII_9.0/Digital_Logic /DE1/Tutorials/Verilog/ ModelSim Altera Starter Edition Links   alone/10.0_modelsim_ase_windows_rev2.exe alone/10.0_modelsim_ase_windows_rev2.exe  ( SWD-MDS-ASE-65E-100-PC&l=en) ( SWD-MDS-ASE-65E-100-PC&l=en

Next Discussion Class  DE1 Installation Tutorial  1.6. Connect board to your computer using the USB cable. Your computer should automatically install the drivers for the USB Blaster. If you need to manually specify the location for the driver, it should be in your quartus II folder under drivers, so when Windows propmts you to add the new hardware, go to c:\altera\90\quartus\drivers\usb- blaster\. Check out DE1 installation tutorialif you have problems with this partDE1 installation tutorial  Lab – 1 Assignment