S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 25: Sequential Circuit Design (3/3) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07 Time Borrowing  In a flop-based system: –Data launches on one rising edge –Must setup before next rising edge –If it arrives late, system fails –If it arrives early, time is wasted –Flops have hard edges  In a latch-based system –Data can pass through latch while transparent –Long cycle of logic can borrow time into next –As long as each loop completes in one cycle

S. Reda EN160 SP’07 Last lecture We talked about two things: –Maximum propagation delay and relationship with clock period and setup time –Minimum (contamination) delay and relationship with hold time

S. Reda EN160 SP’07 Time borrowing illustrated

S. Reda EN160 SP’07 How much can we borrow? 2-Phase Latches Pulsed Latches

S. Reda EN160 SP’07 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time –Decreases maximum propagation delay –Increases minimum contamination delay –Decreases time borrowing

S. Reda EN160 SP’07 Skew: flip-flops

S. Reda EN160 SP’07 Skew: 2-phase latches

S. Reda EN160 SP’07 Skew is not always bad! (Useful Skew) FF i FF j FF k dmax =8ns d max =10ns sisi sjsj  Zero clock skew (s i =0 & s j = 0)  clock period = 10ns, f max = 100MHz  S i = 0 s j = 1ns  clock period = 9ns, f max = 111MHz (no timing violations)  S i = 0 s j = 2ns  clock period = 8ns, f max = 125MHz (no timing violations)  Introducing skew also helps minimize the simultaneous switching of FFs  less load on the P/G network

S. Reda EN160 SP’07 We are done with the main sections of chapter 7 7.1/7.2/7.3 HW5: –Exercises: 7.2, 7.4, 7.6, 7.10 –Due Date: Wed 11 th of April

S. Reda EN160 SP’07 Project Entire class will collaborate on designing a simple MIPS CPU I will go through the CPU description next time in class Today, we can get a head start by working on designing the standard cell library

S. Reda EN160 SP’07 Standard cell design Main standard cells: –Inverter (done) –Tri-state buffer –2-input and 3-input NAND –2-input and 3-input NOR –2-input XOR –2x1 MUX –Latch/FlipFlop –AOI Expected height 70λ (give or take )

S. Reda EN160 SP’07 Required tasks I will distribute the template library as well as the clean 0.5AMI Tanner technology files. Each person required to design a cell. –On Monday April 9 before class, deliver your cells to the library Integrator, together with half a page of text that describes: Cell layout Functional verification diagrams from SPICE simulations Delay and power estimates, Library Integrator will make copy all cells into the same library file (make sure they all comply with standard) and create one text file from all input descriptions. Integrator will iterate with any persons that have design problems. –Deadline for library integrator is Wed April 11.

S. Reda EN160 SP’07 Cell Design Methodology New library has slightly different rules than before I designed an inverter as a guideline Let’s have power lines on metal 1 horizontally and input/output lines vertically on metal 2