San Jose State University Department of Electrical Engineering 4-BIT SERIAL TO PARALLEL CONVERTER EE 166, CMOS DIGITAL INTEGRATED CIRCUIT FINAL PROJECT GROUP MEMBERS: DONG TIEU NGHINH TRAN SPRING 2002

PRESENTATION OVERVIEW Introduction Specification Design Principle Conclusion

INTRODUCTION DESIGN: A serial data stream and convert it to and output parallel data APPLICATION: A/D Converter

SPECIFICATION Minimize the clock skew Worst case power used < 500mW V switchingTH =2.5 V for low and high logic states Area < 40mil 2 Able to drive a 10pF load at 25 Mhz

DESIGN PRINCIPLE

SCHEMATIC

SUPPER BUFFER LAYOUT

SUPPER BUFFER WAVEFORM

CIRCUIT LAYOUT

CIRCUIT WAVEFORM

CONCLUSIONS Reasonable area Finished 2/3 rd project Worked with 2 clock cycles Met speed requirement * Problems: Not work every 4 clock cycles. * Modify: Adding T FF’s to control clock cycle