Counters Discussion 12.1 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

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Presentation transcript:

Counters Discussion 12.1 Example 33

Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter

3-Bit, Divide-by-8 Counter

Divide-by-8 Counter s s s s s s s s State q2 q1 q0 D2 D1 D0 Present state Next state

Divide-by-8 Counter q2 q1 q D2 D2 = ~q2 & q1 & q0 | q2 & ~q1 | q2 & ~q0 s s s s s s s s State q2 q1 q0 D2 D1 D0 Present state Next state

Divide-by-8 Counter q2 q1 q D1 D1 = ~q1 & q0 | q1 & ~q0 s s s s s s s s State q2 q1 q0 D2 D1 D0 Present state Next state

Divide-by-8 Counter q2 q1 q D0 D0 = ~q0 s s s s s s s s State q2 q1 q0 D2 D1 D0 Present state Next state

Divide-by-8 Counter A Divide by 8 counter circuit using D Flip-flops

module count3a ( input wire clr, input wire clk, output reg [2:0] q ); wire [2:0] D ; assign D[2] = ~q[2] & q[1] & q[0] | q[2] & ~q[1] | q[2] & ~q[0]; assign D[1] = ~q[1] & q[0] | q[1] & ~q[0]; assign D[0] = ~q[0]; // Three D flip-flops clk or posedge clr) if(clr == 1) q <= 0; else q <= D; endmodule

count3a Simulation

Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter

3-Bit Counter clk or posedge clr) begin if(clr == 1) q <= 0; else q <= q + 1; end Behavior count3 clr clk Q[2:0]

module count3b ( input wire clr, input wire clk, output reg [2:0] q ); // 3-bit counter clk or posedge clr) begin if(clr == 1) q <= 0; else q <= q + 1; end endmodule count3b.v Asynchronous clear Output count increments on rising edge of clk

count3b Simulation

Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter

module mod5cnt ( input wire clr, input wire clk, output reg [2:0] q ); // modulo-5 counter clk or posedge clr) begin if(clr == 1) q <= 0; else if(q == 4) q <= 0; else q <= q + 1; end endmodule

mod5cnt Simulation

Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter

module counter #(parameter N = 8) (input wire clr, input wire clk, output reg [N-1:0] q ); // N-bit counter clk or posedge clr) begin if(clr == 1) q <= 0; else q <= q + 1; end endmodule defparam cnt16.N = 16; counter cnt16(.clr(clr),.clk(clk),.q(q));

counter Simulation N = 8