CS Spring 2007 – Lecture #1: Introduction - 1 Welcome to EECS 150: Components and Design Techniques for Digital Systems zCourse staff yRandy Katz (Instructor), Jeff Kalvass (Admin Head TA), Allen Lee/Neil Warren (Project Co-Head TAs) yTeaching Assistants: Shah Bawany, Young Lee, Brent Mochizuki, Laura Pelton yReaders: Katie Chou zCourse web yinst.eecs.Berkeley.edu/~eecs150 (coming soon) zThis week yWhat is logic design? yWhat is digital hardware? yWhat will we be doing in this class? yQuick Review yClass administration, overview of course web, and logistics

CS Spring 2007 – Lecture #1: Introduction - 2 Why Are We Here? zImplementation basis for modern computing devices yConstructing large systems from small components yAnother view of a computer: controller + datapath zInherent parallelism in hardware yParallel computation beyond 61C zCounterpoint to software design yFurthering our understanding of computation

CS Spring 2007 – Lecture #1: Introduction - 3 We Will Learn in EECS 150 … zLanguage of logic design yLogic optimization, state, timing, CAD tools zConcept of state in digital systems yAnalogous to variables and program counters in software systems zHardware system building yDatapath + control = digital systems zHardware system design methodology yHardware description languages: Verilog yTools to simulate design behavior: output = function (inputs) yLogic compilers synthesize hardware blocks of our designs yMapping onto programmable hardware (code generation) zContrast with software design yBoth map specifications to physical devices yBoth must be flawless…the price we pay for using discrete math

CS Spring 2007 – Lecture #1: Introduction - 4 What is Logic Design? zWhat is design? yGiven problem spec, solve it with available components yWhile meeting quantitative (size, cost, power) and qualitative (beauty, elegance) zWhat is logic design? yChoose digital logic components to perform specified control, data manipulation, or communication function and their interconnection yWhich logic components to choose? Many implementation technologies (fixed-function components, programmable devices, individual transistors on a chip, etc.) yDesign optimized/transformed to meet design constraints

CS Spring 2007 – Lecture #1: Introduction - 5 Source: Microsoft Encarta sense drive AND What is Digital Hardware? zDevices that sense/control wires carrying digital values (physical quantity interpreted as “0” or “1”) yDigital logic: voltage 2.0v is “1” yPair of wires where “0”/“1” distinguished by which has higher voltage (differential) yMagnetic orientation signifies “0” or “1” zPrimitive digital hardware devices yLogic computation devices (sense and drive) xTwo wires both “1” - make another be “1” (AND) xAt least one of two wires “1” - make another be “1” (OR) xA wire “1” - then make another be “0” (NOT) yMemory devices (store) xStore a value xRecall a value previously stored

CS Spring 2007 – Lecture #1: Introduction - 6 What is the Current State of Digital Design? zChanges in industrial practice yLarger designs yShorter time to market yCheaper products zScale yPervasive use of computer-aided design tools over hand methods yMultiple levels of design representation zTime yEmphasis on abstract design representations yProgrammable rather than fixed function components yAutomatic synthesis techniques yImportance of sound design methodologies zCost yHigher levels of integration yUse of simulation to debug designs $39 DVD

CS Spring 2007 – Lecture #1: Introduction - 7 Parts Cost: $25 Sales Price: $30!

CS Spring 2007 – Lecture #1: Introduction - 8 New ability: perform logic design with computer-aided design tools, validating that design via simulation, and mapping its implementation into programmable logic devices; Appreciating the advantages/disadvantages hw vs. sw implementation CS 150: Concepts/Skills/Abilities zBasics of logic design (concepts) zSound design methodologies (concepts) zModern specification methods (concepts) zFamiliarity with full set of CAD tools (skills) zAppreciation for differences and similarities (abilities) in hardware and software design

CS Spring 2007 – Lecture #1: Introduction - 9 Administrative Details zSee course web page for gory details! yT Th 2-3:30 course lecture, F 2-3 lab lecture y1x3 hour lab, 1x1=hour discussion per week yNo labs or discussions first week! zGrading yMidterm Exams (15 Feb, 22 Mar): 20% yFinal Exam (11 May, 12:30-3:30): 20% yLabs (1-5): 15% yProject (Videoconferencing, Checkpoints 0-4): 30% yHomeworks (10 problem sets): 10% yIn-class pop quizzes: 5% xFirst one NOW: Diagnostic Quiz (not graded!)

CS Spring 2007 – Lecture #1: Introduction - 10 Administrative Details zNo labs or discussion during the first week! zAll lab lectures, labs, and discussion sections take place in 125 Cory Hall (despite what the course schedule says!) zLab Lecture PM zLabs yTu, W, 11-2 PM yTu, W, 5-8 PM y16 student limit per lab yStudents assigned to cancelled F lab have preference for a new section yWait listed students able to take T Th morning labs or W evening lab have preference zDiscussion Sections yTh 4-5 PM, F 10-11, F yOK to attend any section

CS Spring 2007 – Lecture #1: Introduction - 11 Course Project: Videoconferencing System zNot quite this … but: yVideo camera capture yCRT video display ySerial compressed video 2-way transmission between two stations y(no audio this semester) yImplemented in a Xilinx FPGA on the Calinx boards you will use in lab yGroups of two

CS Spring 2007 – Lecture #1: Introduction - 12 Course Project: Videoconferencing System Checkpoint #4 SDRAM Display Camera Comp Decomp SDRAM Display Camera Comp Decomp Serial Transmission

CS Spring 2007 – Lecture #1: Introduction - 13 Calinx EECS 150 Lab/Project Protoboard Flash Card & Micro-drive Port Video Encoder & Decoder AC ’97 Codec & Power Amp Video & Audio Ports Four 100 Mb Ethernet Ports 8 Meg x 32 SDRAM Quad Ethernet Transceiver Xilinx Virtex 2000E Seven Segment LED Displays Prototype Area

CS Spring 2007 – Lecture #1: Introduction - 14 Computation: Abstract vs. Implementation zComputation as a mental exercise (paper, programs) zvs. implementation with physical devices using voltages to represent logical values zBasic units of computation: yRepresentation:"0", "1" on a wire set of wires (e.g., for binary integers) yAssignment:x = y yData operations:x + y – 5 yControl: Sequential statements: A; B; C Conditionals:if x == 1 then y Loops:for ( i = 1 ; i == 10, i++) Procedures:A; proc(...); B; zStudy how these are implemented in hardware and composed into computational structures

CS Spring 2007 – Lecture #1: Introduction - 15 Close switch (if A is “1” or asserted) and turn on light bulb (Z) AZ Open switch (if A is “0” or unasserted) and turn off light bulb (Z) Switches: Basic Element of Physical Implementations zImplementing a simple circuit (arrow shows action if wire changes to “1”): Z  A A Z

CS Spring 2007 – Lecture #1: Introduction - 16 AND OR Z  A and B Z  A or B A B A B Switches (cont’d) zCompose switches into more complex ones (Boolean functions):

CS Spring 2007 – Lecture #1: Introduction - 17 Switching Networks zSwitch settings yDetermine whether conducting path exists to light the bulb zTo build larger computations yUse bulb (output of the network) to set other switches (inputs to another network) zInterconnect switching networks yConstruct larger switching networks, i.e., connect outputs of one network to the inputs of the next.

CS Spring 2007 – Lecture #1: Introduction - 18 Transistor Networks zModern digital systems designed in CMOS yMOS: Metal-Oxide on Semiconductor yC for complementary: normally-open and normally-closed switches zMOS transistors act as voltage-controlled switches ySimilar, though easier to work with, than relays.

CS Spring 2007 – Lecture #1: Introduction - 19 n-channel open when voltage at G is low closes when: voltage(G) > voltage (S) +  p-channel closed when voltage at G is low opens when: voltage(G) < voltage (S) –  MOS Transistors zThree terminals: drain, gate, and source ySwitch action: if voltage on gate terminal is (some amount) higher/lower than source terminal then conducting path established between drain and source terminals G SD G SD

CS Spring 2007 – Lecture #1: Introduction v X Y 0 volts xy 3 volts 0v what is the relationship between x and y? MOS Networks

CS Spring 2007 – Lecture #1: Introduction - 21 xy z 0 volts 3 volts 0 volts 3 volts 0 volts 3 volts what is the relationship between x, y and z? Two Input Networks 3v XY 0v Z 3v XY 0v Z

CS Spring 2007 – Lecture #1: Introduction - 22 scope of CS 150 Representation of Digital Designs zPhysical devices (transistors, relays) zSwitches zTruth tables zBoolean algebra zGates zWaveforms zFinite state behavior zRegister-transfer behavior zConcurrent abstract specifications more depth than 61C focus on building systems

CS Spring 2007 – Lecture #1: Introduction - 23 Technology State 0 State 1 Relay logicCircuit OpenCircuit Closed CMOS logic volts volts Transistor transistor logic (TTL) volts volts Fiber OpticsLight offLight on Dynamic RAMDischarged capacitorCharged capacitor Nonvolatile memory (erasable)Trapped electronsNo trapped electrons Programmable ROMFuse blownFuse intact Bubble memoryNo magnetic bubbleBubble present Magnetic diskNo flux reversalFlux reversal Compact discNo pitPit Mapping Physical to Binary World

CS Spring 2007 – Lecture #1: Introduction - 24 inputsoutputs system Combinational vs. Sequential Digital Circuits zSimple model of a digital system is a unit with inputs and outputs: zCombinational means "memory-less" yDigital circuit is combinational if its output values only depend on its inputs

CS Spring 2007 – Lecture #1: Introduction - 25 Combinational Logic Symbols zCommon combinational logic systems have standard symbols called logic gates yBuffer, NOT yAND, NAND yOR, NOR Z A B Z Z A A B Easy to implement with CMOS transistors (the switches we have available and use most)

CS Spring 2007 – Lecture #1: Introduction - 26 Sequential Logic zSequential systems yExhibit behaviors (output values) that depend on current as well as previous inputs zTime response of real circuits are sequential yOutputs do not change instantaneously after an input change yWhy not, and why is it then sequential? zFundamental abstraction of digital design is to reason (mostly) about steady-state behaviors yExamine outputs only after sufficient time has elapsed for the system to make its required changes and settle down

CS Spring 2007 – Lecture #1: Introduction - 27 Synchronous Sequential Digital Systems zCombinational outputs depend only on current inputs yAfter sufficient time has elapsed zSequential circuits have memory yEven after waiting for transient activity to finish zSteady-state abstraction: most designers use it when constructing sequential circuits yMemory of system is its state yChanges in system state only allowed at specific times controlled by external periodic signal (the clock) yClock period is time between state changes sufficiently long so that system reaches steady-state before next state change

CS Spring 2007 – Lecture #1: Introduction - 28 B A C Clock Distinction: Combinational vs. Sequential Logic zCombinational: yInput A, B yWait for clock edge yObserve C yWait for another clock edge yObserve C again: will stay the same zSequential: yInput A, B yWait for clock edge yObserve C yWait for another clock edge yObserve C again: may be different

CS Spring 2007 – Lecture #1: Introduction - 29 Example: Combinational Design zCalendar subsystem: number of days in a month (to control watch display) yUsed in controlling the display of a wrist-watch LCD screen yInputs: month, leap year flag yOutputs: number of days

CS Spring 2007 – Lecture #1: Introduction - 30 Implementation in Software integer number_of_days (month, leap_year_flag) { switch (month) { case 1: return (31); case 2: if (leap_year_flag == 1) then return (29) else return (28); case 3: return (31);... case 12: return (31); default: return (0); }

CS Spring 2007 – Lecture #1: Introduction - 31 leap month d28d29d30d31 monthleapd28d29d30d ––––– 0001– – – – – – – – – – – ––––– 111–––––– Implementation as a Combinational Digital System zEncoding: yHow many bits for each input/output? yBinary number for month yFour wires for 28, 29, 30, and 31 zBehavior: yCombinational yTruth table specification

CS Spring 2007 – Lecture #1: Introduction - 32 Combinational Example (cont’d) zTruth-table to logic to switches to gates yd28 = 1 when month=0010 and leap=0 yd28 = m8'm4'm2m1'leap' yd31 = 1 when month=0001 or month=0011 or... month=1100 yd31 = (m8'm4'm2'm1) + (m8'm4'm2m1) +... (m8m4m2'm1') yd31 = can we simplify more? monthleapd28d29d30d – – – – ––––– 111–––––– 0000––––– symbol for and symbol for or symbol for not

CS Spring 2007 – Lecture #1: Introduction - 33 Combinational Example (cont’d) zd28 = m8'm4'm2m1'leap’ zd29 = m8'm4'm2m1'leap zd30 = (m8'm4m2'm1') + (m8'm4m2m1') + (m8m4'm2'm1) + (m8m4'm2m1) zd31 = (m8'm4'm2'm1) + (m8'm4'm2m1) + (m8'm4m2'm1) + (m8'm4m2m1) + (m8m4'm2'm4') + (m8m4'm2m1') + (m8m4m2'm1')

CS Spring 2007 – Lecture #1: Introduction - 34 Combinational Example (cont’d) zd28 = m8'm4'm2m1'leap’ zd29 = m8'm4'm2m1'leap zd30 = (m8'm4m2'm1') + (m8'm4m2m1') + (m8m4'm2'm1) + (m8m4'm2m1) zd31 = (m8'm4'm2'm1) + (m8'm4'm2m1) + (m8'm4m2'm1) + (m8'm4m2m1) + (m8m4'm2'm4') + (m8m4'm2m1') + (m8m4m2'm1')

CS Spring 2007 – Lecture #1: Introduction - 35 Example: Sequential Design zDoor combination lock: yPunch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset yInputs: sequence of input values, reset yOutputs: door open/close yMemory: must remember combination or always have it available as an input

CS Spring 2007 – Lecture #1: Introduction - 36 Implementation in Software integer combination_lock ( ) { integer v1, v2, v3; integer error = 0; static integer c[3] = 3, 4, 2; while (!new_value( )); v1 = read_value( ); if (v1 != c[1]) then error = 1; while (!new_value( )); v2 = read_value( ); if (v2 != c[2]) then error = 1; while (!new_value( )); v3 = read_value( ); if (v2 != c[3]) then error = 1; if (error == 1) then return(0); else return (1); }

CS Spring 2007 – Lecture #1: Introduction - 37 Implementation as a Sequential Digital System zEncoding: yHow many bits per input value? yHow many values in sequence? yHow do we know a new input value is entered? yHow do we represent the states of the system? zBehavior: yClock wire tells us when it’s ok to look at inputs (i.e., they have settled after change) ySequential: sequence of values must be entered ySequential: remember if an error occurred yFinite-state specification reset value open/closed new clock state

CS Spring 2007 – Lecture #1: Introduction - 38 closed C1=value & new C2=value & new C3=value & new C1!=value & new C2!=value & new C3!=value & new closed reset not new S1S2S3OPEN ERR open Sequential Example (cont’d): Abstract Control zFinite state diagram yStates: 5 states xRepresent point in execution of machine xEach state has outputs yTransitions: 6 from state to state, 5 self transitions, 1 global xChanges of state occur when clock says it’s ok xBased on value of inputs yInputs: reset, new, results of comparisons yOutput: open/closed

CS Spring 2007 – Lecture #1: Introduction - 39 reset open/closed new C1C2C3 comparator value equal multiplexer equal controller mux control clock Sequential Example (cont’d): Datapath vs. Control zInternal structure yData-path xStorage for combination xComparators yControl xFinite state machine controller xControl for data-path xState changes controlled by clock

CS Spring 2007 – Lecture #1: Introduction - 40 closed mux=C1 reset equal & new not equal & new not new S1S2S3OPEN ERR closed mux=C2 equal & new closed mux=C3 equal & new open Sequential Example (cont’d): Finite State Machine zFinite-state machine yRefine state diagram to include internal structure

CS Spring 2007 – Lecture #1: Introduction - 41 resetnewequalstatestatemuxopen/closed 1–––S1C1closed 00–S1S1C1closed 010S1ERR–closed 011S1S2C2closed 00–S2S2C2closed 010S2ERR–closed 011S2S3C3closed 00–S3S3C3closed 010S3ERR–closed 011S3OPEN–open 0 – –OPENOPEN– open 0 – –ERRERR– closed next Sequential Example (cont’d): Finite State Machine zFinite State Machine yGenerate state table (much like a truth-table) closed mux=C1 reset equal & new not equal & new not new S1S2S3OPEN ERR closed mux=C2 equal & new closed mux=C3 equal & new open

CS Spring 2007 – Lecture #1: Introduction - 42 Sequential Example (cont’d): Encoding zEncode state table yState can be: S1, S2, S3, OPEN, or ERR xneeds at least 3 bits to encode: 000, 001, 010, 011, 100 xand as many as 5: 00001, 00010, 00100, 01000, xchoose 4 bits: 0001, 0010, 0100, 1000, 0000 yOutput mux can be: C1, C2, or C3 xneeds 2 to 3 bits to encode xchoose 3 bits: 001, 010, 100 yOutput open/closed can be: open or closed xneeds 1 or 2 bits to encode xchoose 1 bits: 1, 0

CS Spring 2007 – Lecture #1: Introduction - 43 good choice of encoding! mux is identical to last 3 bits of state open/closed is identical to first bit of state Sequential Example (cont’d): Encoding zEncode state table yState can be: S1, S2, S3, OPEN, or ERR xChoose 4 bits: 0001, 0010, 0100, 1000, 0000 yOutput mux can be: C1, C2, or C3 xChoose 3 bits: 001, 010, 100 yOutput open/closed can be: open or closed xChoose 1 bits: 1, 0 resetnewequalstatestatemuxopen/closed 1––– – – – – – – – 1 0 – – – 1 0 – – – 0 next

CS Spring 2007 – Lecture #1: Introduction - 44 reset open/closed newequal controller mux control clock reset open/closed newequal mux control clock comb. logic state Special circuit element, called a register, for remembering inputs when told to by clock Sequential Example (cont’d): Controller Implementation zController Implementation

CS Spring 2007 – Lecture #1: Introduction - 45 system datapath control state registers combinational logic multiplexer comparator code registers registerlogic switching networks Design Hierarchy

CS Spring 2007 – Lecture #1: Introduction - 46 Summary zWhat the entire course is about yConverting solutions to problems into combinational and sequential networks effectively organizing the design hierarchically yDoing so with a modern set of design tools that lets us handle large designs effectively yTaking advantage of optimization opportunities zNow let’s do it again ythis time we'll take the rest of the semester!