FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3

FPGAs and VHDL History of Programmable Logic Devices –PLDs and CPLDs –Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register –Fibonacci Sequence Generator

1975 – Signetics invents the FPLA

1978 – MMI introduces the PAL

1983 – AMD introduces the 22V – Lattice introduces the GAL – an electrically erasable PAL

XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ HQ208 BG352 PQ160 HQ208 BG

Xilinx function blocks –Each contains 18 macro cells –Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs

Architecture of the Xilinx XC95108 CPLD

PLDT-3 Xilinx XC95108 CPLD 7 segment display Switches LEDs Buttons

1985 – Xilinx introduces the LCA (Logic Cell Array) The Xilinx XC3000 CLB (configurable logic block).

Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs) 1991 – Xilinx introduces the XC4000 Architecture XC4003 contained 440,000 transistors 0.7-micron process

XC4000E/X Configurable Logic Blocks 2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function 2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset

Look Up Tables  Capacity is limited by number of inputs, not complexity  Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example: A B C D Z Look Up Table Combinatorial Logic A B C D Z 4-bit address G Func. Gen. G4 G3 G2 G1 WE 2 (2 ) 4 = 64K !

What’s Really In that Chip? CLB (Red) Switch Matrix Long Lines (Purple) Direct Interconnect (Green) Routed Wires (Blue) Programmable Interconnect Points, PIPs (White)

1998 – Xilinx introduces the Virtex®™ FPGA family 0.25-micron process

2003 – Xilinx introduces the Spartan®™-3 family of products This very low-cost product is the world's first 90nm FPGA Very low cost World’s first 90 nm FPGA

Block diagram of Xilinx Spartan IIE FPGA

Each Spartan IIE CLB contains two of these CLB slices

x Xilinx will release the world’s first one-billion transistor device this year

Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE standard specification language (IEEE ) for describing digital hardware used by industry worldwide VHDL enables hardware modeling from the gate level to the system level

Combinational Circuit Example 8-line 2-to-1 Multiplexer 8-line 2 x 1 MUX a(7:0) b(7:0) y(7:0) sel sel y 0 a 1 b

library IEEE; use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux2; An 8-line 2 x 1 MUX a(7:0) b(7:0) y(7:0) sel 8-line 2 x 1 MUX

library IEEE; use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux2; Entity Each entity must begin with these library and use statements port statement defines inputs and outputs

library IEEE; use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) ); end mux2; Entity Mode: in or out Data type: STD_LOGIC, STD_LOGIC_VECTOR(7 downto 0);

architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; Architecture a(7:0) b(7:0) y(7:0) sel 8-line 2 x 1 MUX Note: <= is signal assignment

architecture mux2_arch of mux2 is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2_arch; Architecture entity name process sensitivity list Sequential statements (if…then…else) must be in a process Note begin…end in process Note begin…end in architecture

An 8-line 4 x 1 multiplexer a(7:0) b(7:0) y(7:0) sel(1:0) 8-line 4 x 1 MUX c(7:0) d(7:0) Sely “00”a “01”b “10”c “11”d

An 8-line 4 x 1 multiplexer library IEEE; use IEEE.std_logic_1164.all; entity mux4 is port ( a: in STD_LOGIC_VECTOR (7 downto 0); b: in STD_LOGIC_VECTOR (7 downto 0); c: in STD_LOGIC_VECTOR (7 downto 0); d: in STD_LOGIC_VECTOR (7 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (7 downto 0) ); end mux4;

Example of case statement architecture mux4_arch of mux4 is begin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process; end mux4_arch; Must include ALL posibilities in case statement Note implies operator => Sely “00”a “01”b “10”c “11”d

An Adder -- Title: adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity adder is generic(width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end adder; architecture adder_arch of adder is begin add1: process(a, b) begin y <= a + b; end process add1; end adder_arch; Note: + sign synthesizes an n-bit full adder!

Binary-to-BCD Converter

-- Title: Binary-to-BCD Converter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity binbcd is port ( B: in STD_LOGIC_VECTOR (7 downto 0); P: out STD_LOGIC_VECTOR (9 downto 0) ); end binbcd;

architecture binbcd_arch of binbcd is begin bcd1: process(B) variable z: STD_LOGIC_VECTOR (17 downto 0); begin for i in 0 to 17 loop z(i) := '0'; end loop; z(10 downto 3) := B; for i in 0 to 4 loop if z(11 downto 8) > 4 then z(11 downto 8) := z(11 downto 8) + 3; end if; if z(15 downto 12) > 4 then z(15 downto 12) := z(15 downto 12) + 3; end if; z(17 downto 1) := z(16 downto 0); end loop; P <= z(17 downto 8); end process bcd1; end binbcd_arch;

A Register -- A width-bit register library IEEE; use IEEE.std_logic_1164.all; entity reg is generic(width: positive); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (width-1 downto 0) ); end reg;

architecture reg_arch of reg is begin process(clk, clr) begin if clr = '1' then for i in width-1 downto 0 loop q(i) <= '0'; end loop; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end process; end reg_arch; Register architecture Infers a flip-flop for all outputs (q)

Fibonacci Sequence -- Title: Fibonacci Sequence library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; entity fib is port( clr : in std_logic; clk : in std_logic; P : out std_logic_vector(9 downto 0) ); end fib; P

architecture fib_arch of fib is component adder generic( width : POSITIVE); port( a : in std_logic_vector((width-1) downto 0); b : in std_logic_vector((width-1) downto 0); y : out std_logic_vector((width-1) downto 0)); end component; component reg generic( width : POSITIVE); port( d : in std_logic_vector((width-1) downto 0); load : in std_logic; clr : in std_logic; set : in std_logic; clk : in std_logic; q : out std_logic_vector((width-1) downto 0)); end component; Declare components

component binbcd port( B : in std_logic_vector(7 downto 0); P : out std_logic_vector(9 downto 0)); end component; signal r, s, t: std_logic_vector(7 downto 0); signal one, zero: std_logic; constant bus_width: positive := 8;

begin one <= '1'; zero <= '0'; U1: adder generic map(width => bus_width) port map (a => t, b => r, y => s); R1: reg generic map(width => bus_width) port map (d => r, load =>one, clr => zero, set => clr, clk =>clk, q => t); W: reg generic map(width => bus_width) port map (d => s, load => one, clr => clr, set => zero, clk =>clk, q => r); U2: binbcd port map (B => r, P => P); end fib_arch; Wire up the circuit

Fibonacci Sequence Works!