ECE 665 - Routing 1 ECE 665 Spring 2004 ECE 665 Spring 2004 Computer Algorithms with Applications to VLSI CAD Channel Routing Global Routing.

Slides:



Advertisements
Similar presentations
VLSI DESIGN & COMPARABILITY GRAPHS By Deepak Katta.
Advertisements

ECE Longest Path dual 1 ECE 665 Spring 2005 ECE 665 Spring 2005 Computer Algorithms with Applications to VLSI CAD Linear Programming Duality – Longest.
An Introduction to Channel Routing
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Ch.7 Layout Design Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology.
5-1 Chapter 5 Tree Searching Strategies. 5-2 Satisfiability problem Tree representation of 8 assignments. If there are n variables x 1, x 2, …,x n, then.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Rajat K. Pal. Chapter 3 Emran Chowdhury # P Presented by.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 11 - Combinational.
Multi-Layer Channel Routing Complexity and Algorithm - Rajat K. Pal Md. Jawaherul Alam # P Presented by Section 5.3: NP-completeness of Multi-Layer.
A Framework for Track Assignment Presented by: Kaiser Newaj Asif Multi-Layer Routing (Extensions of the TAH Framework)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 21: April 15, 2009 Routing 1.
VLSI Routing. Routing Problem  Given a placement, and a fixed number of metal layers, find a valid pattern of horizontal and vertical wires that connect.
A General Framework for Track Assignment in Multilayer Channel Routing (Multi layer routing) -VLSI Layout Algorithm KAZY NOOR –E- ALAM SIDDIQUEE
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 19: April 9, 2008 Routing 1.
3.3 Multi-Layer V i+1 H i Channel Routing Presented by Zulfiquer Md. Mizanur Rhaman Student # p.
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
3.3 Multi-Layer V i+1 H i Channel Routing Presented by Md. Shaifur Rahman Student #
A Specialized A* Algorithm. Specialized A* Algorithm As soon as a goal node is found, we may stop and return an optimal solution. In ordinary A* algorithm,
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
Chapter 5: Computational Complexity of Area Minimization in Multi-Layer Channel Routing and an Efficient Algorithm Presented by Md. Raqibul Hasan Std No.
7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.
Routing 2 Outline –Maze Routing –Line Probe Routing –Channel Routing Goal –Understand maze routing –Understand line probe routing.
Chip Planning 1. Introduction Chip Planning:  Deals with large modules with −known areas −fixed/changeable shapes −(possibly fixed locations for some.
General Routing Overview and Channel Routing
Introduction to Routing. The Routing Problem Apply after placement Input: –Netlist –Timing budget for, typically, critical nets –Locations of blocks and.
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
9/4/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (I)
Escape Routing For Dense Pin Clusters In Integrated Circuits Mustafa Ozdal, Design Automation Conference, 2007 Mustafa Ozdal, IEEE Trans. on CAD, 2009.
Global Routing. Global routing:  To route all the nets, should consider capacities  Sequential −One net at a time  Concurrent −Order-independent 2.
Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Standard cell-based layout. n Channel routing. n Simulation.
Global Routing.
1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.
FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.
Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Layouts for logic networks. n Channel routing. n Simulation.
Modern VLSI Design 3e: Chapters 1-3 week12-1 Lecture 30 Scale and Yield Mar. 24, 2003.
Bus-Driven Floorplanning Hua Xiang*, Xiaoping Tang +, Martin D. F. Wong* * Univ. Of Illinois at Urbana-Champaign + Cadence Design Systems Inc.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.
Kwangsoo Han‡, Andrew B. Kahng‡† and Hyein Lee‡
Placement. Physical Design Cycle Partitioning Placement/ Floorplanning Placement/ Floorplanning Routing Break the circuit up into smaller segments Place.
Fishbone: A Block-Level Placement and Routing Scheme Fan Mo and Robert K. Brayton EECS, UC Berkeley.
6/5/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (III)
A Negotiated Congestion based Router for Simultaneous Escape Routing Q.Ma, T.Yan and Martin D.F. Wong Department of Electrical and Computer Engineering.
Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Layouts for logic networks. n Channel routing. n Simulation.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 13: February 20, 2002 Routing 1.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 13: March 3, 2015 Routing 1.
Detailed Routing مرتضي صاحب الزماني.
Graph Coloring. Vertex Coloring problem in VLSI routing channels Standard cells Share a track Minimize channel width- assign horizontal Metal wires to.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
1 L25 : Crosstalk-Concerned Physical Design (2) Jun Dong Cho Sungkyunkwan Univ. Dept. ECE Homepage :
Routing Topology Algorithms Mustafa Ozdal 1. Introduction How to connect nets with multiple terminals? Net topologies needed before point-to-point routing.
مرتضي صاحب الزماني 1 Detailed Routing. مرتضي صاحب الزماني 2 Greedy Routing “ A greedy channel router ”, Rivest, Fiduccia, Proceedings of the nineteenth.
2/27/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (II)
An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.
EE4271 VLSI Design VLSI Channel Routing.
CALTECH CS137 Fall DeHon 1 CS137: Electronic Design Automation Day 21: November 28, 2005 Routing 1.
VLSI Physical Design Automation
VLSI Physical Design Automation
VLSI Physical Design Automation
VLSI Quadratic Placement
ESE535: Electronic Design Automation
By Santhosh Reddy Katkoori
Iterative Deletion Routing Algorithm
EE4271 VLSI Design, Fall 2016 VLSI Channel Routing.
Detailed Routing مرتضي صاحب الزماني.
VLSI Physical Design Automation
1.6 Linear Programming Pg. 30.
Under a Concurrent and Hierarchical Scheme
Presentation transcript:

ECE Routing 1 ECE 665 Spring 2004 ECE 665 Spring 2004 Computer Algorithms with Applications to VLSI CAD Channel Routing Global Routing

ECE Routing 2 Channel Routing Problem Assume uniform net width: track Two layers of interconnect: – –L1 for horizontal nets – –L2 for vertical connections Represent each net segment as an interval, indicating the terminal connections up  or down  Given a rectangular channel with terminals located on both sides of the channel, and a set of nets to be routed, place the nets in the channel to minimize its width [Has71,Yos84]. Formulation:

ECE Routing 3 Interval Graph V = {net segments} E = horizontal relations between the nets: – –(v i, v j )  E iff nets n i and n j overlap The density of IG (max clique size): d max Channel density: d  d max Define an Interval Graph, IG(V,E) In general, finding max clique size is NP-complete!

ECE Routing 4 Channel Routing 1 2 Define routing regions = channelsDefine routing regions = channels Routing channel 1 2

ECE Routing 5 Perform routing of nets to minimize channel widthPerform routing of nets to minimize channel width 1 2 Channel Routing 1 2

ECE Routing 6 Move blocks at a minimum distance (channel width)Move blocks at a minimum distance (channel width) 1 2 Channel Routing 1 2

ECE Routing 7 Feasibility of Channel Routing What happens when blocks move apart, when more space is neededWhat happens when blocks move apart, when more space is needed

ECE Routing 8 Routing Violation Nets overlap because of change in relative pin position Pins can move away but not sidewaysPins can move away but not sideways 1 2 Problem: net overlap 1 2

ECE Routing 9 Ordering of Routing Channels Need to process channels in certain order, so that the routing of individual channels need not be redone Does such an ordering exist ? Process first Process this channel next

ECE Routing 10 Channel Ordering Channel ordering = topological sorting of OG(V, E) Create Channel Order Graph OG(V,E) V = {channels} E = “dead-end” relations between channels: (c i, c k )  E if c i  c k

ECE Routing 11 Channel Ordering Condition Every layout is inherently routable iff its Channel Order Graph OG(V,E) is acyclic [Liu 82] A D B C E FG

ECE Routing 12 Breaking Cyclic Constraints A C B E D L L Break cyclic constraint by creating an L channel