IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2002 -

Slides:



Advertisements
Similar presentations
Page 1 Group/Presentation Title Agilent Restricted 8 January 2014 Remove this slide before customer presentation This is the slide set that should be used.
Advertisements

International Graduate School Cottbus / IHP microelectronics Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt.
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
B. BOUDJELIDA 2 nd SKADS Workshop October 2007 Large gate periphery InGaAs/InAlAs pHEMT: Measurement and Modelling for LNA fabrication B. Boudjelida,
R. van Langevelde, A.J. Scholten Philips Research, The Netherlands
EKV3 design kit for 110nm RF-CMOS
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
Metal Oxide Semiconductor Field Effect Transistors
IHP 2 Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany © 2005.
Institut für Theoretische Elektrotechnik Dipl.-Ing. Jan Bremer Large Signal Modeling of Inversion-Mode MOS Varactors in VCOs MOS-AK Meeting April.
PSPICE Tutorial. Introduction SPICE (Simulation Program for Integrated Circuits Emphasis) is a general purpose analog circuit simulator that is used to.
Comparison of the Behavior of MOSFET Transistors Described in Hardware Description Languages Aravind Gurumurthy M.S Thesis Defense Presentation Committee.
Using Spice in Lab Practicing for Analog ASIC Design Goran Jovanović, Faculty of Electronic Engineering University of Niš Serbia and Montenegro.
Bertrand Ardouin Thomas Zimmer XMOD Technologies: Hicum toolkit & extraction services HICUM Workshop, September 2002, Monterey.
SOI BiCMOS  an Emerging Mixed-Signal Technology Platform
Design of RF CMOS Low Noise Amplifiers Using a Current Based MOSFET Model Virgínia Helena Varotto Baroncini Oscar da Costa Gouveia Filho.
General Overview of Modelling and Test Methodology of HV MOSFET J Rhayem, B Desoete, S. Frere, R. Gillon AMIS Semiconductor Belgium BVBA Westerring 15,
1 Sachs et. al. IEEE Trans. Nuclear Science NS-31, 1249 (1984) Threshold Shift vs Gate Oxide Thickness Hole removal process by tunneling in thin-oxide.
Characterization of two Field-Plated GaN HEMT Structures
MOSFET modeling for RF circuit design/MOS-AK Workshop 2004/Sep.20 Nobuyuki Itoh/Toshiba MOSFET modeling for RF circuit design Nobuyuki Itoh Semiconductor.
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
LDMOS for RF Power Amplifiers
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
MOS-AK, San Francisco, Dec. 13, The HiSIM Family of Compact-Models for Integrated Devices H. J. Mattausch, N. Sadachika, M. Miyake, H. Kikuchihara,
Extension for High-Voltage Lateral DMOS Transistors
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering Circuit Design Verification.
Digital Integrated Circuits© Prentice Hall 1995 Introduction The Devices.
I3T Modeling flow : September-2011 Modeling flow and models improvement for I3T ON Semiconductor technologies Petr Betak, Petr Zavrel, Lenka Sochova, Jan.
MOS Capacitors MOS capacitors are the basic building blocks of CMOS transistors MOS capacitors distill the basic physics of MOS transistors MOS capacitors.
Self-heating investigation of bulk and SOI transistors
A Bias-Dependent Equivalent-Circuit Model of Evanescently Coupled Photodiode (ECPD) Advisers : J.- W. Shi, Y.- J. Chan Student : Y.- S. Wu.
*F. Adamu-Lema, G. Roy, A. R. Brown, A. Asenov and S. Roy
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved IHP Technology Roadmap Update and Future.
Seoul National University CMOS for Power Device CMOS for Power Device 전파공학 연구실 노 영 우 Microwave Device Term Project.
MOSFET Modeling for RF Circuit Design Kenneth Yau MASc Candidate Department of Electrical and Computer Engineering University of Toronto Toronto, ON M54.
Achieve a New Type Frequency Divider Circuit and Application By MOS-HBT-NDR Y.K. LI, K.J. Gan, C. S. Tsai, P.H. Chang and Y. H. Chen Department of Electronic.
S. FREGONESE 19 juin 2004 HICUM WORKSHOP /25 Scalable bipolar transistor modelling with HICUM L0 S. Frégonèse, D. Berger *, T. Zimmer, C. Maneux,
Microwave Traveling Wave Amplifiers and Distributed Oscillators ICs in Industry Standard Silicon CMOS Kalyan Bhattacharyya Supervisors: Drs. J. Mukherjee.
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
ITRS: RF and Analog/Mixed- Signal Technologies for Wireless Communications Nick Krajewski CMPE /16/2005.
A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio
Fabrication of CMOS Imagers
Bertrand Ardouin Thomas Zimmer Michael Schröter XMOD Technologies: Hicum toolkit & extraction services HICUM Workshop, June 6 - 7, Dresden.
SiGe Meeting, Geneva 1 Fast Silicon Sensors. SiGe Meeting, Geneva Fast sensors 2 N-well P-substrate Time.
Modeling Intermodulation Distortion in HEMT and LDMOS Devices Using a New Empirical Non-Linear Compact Model Toufik Sadi and Frank Schwierz Department.
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
Delivering Success. Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66 By Alhan Farhanah, Mohd Shahrul Amran, Albert Victor Kordesch Device.
1 High Frequency Model of Sub-100nm High-k RF CMOS ○M. Nakagawa 1, J.Song 1, Y. Nara 2, M. Yasuhira 2 *, F. Ohtsuka 2, T. Arikado 2 **, K. Nakamura 2,
Minimization in variation of output characteristics of a SOI MOS due to Self Heating Sahil M. BansalD.Nagchaudhuri B.E. Final Year, Professor, Electronics.
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
Chapter 2 MOS Transistor Theory. NMOS Operation Region.
Use of Data Analysis and TCAD Simulations to Understand the Characteristics and Reliability of High Voltage MOS Transistors Jone F. Chen Department of.
Ekaterina Laskin, Sean T. Nicolson, Sorin P. Voinigescu
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
A 3-V Fully Differential Distributed Limiting Driver for 40 Gb/s Optical Transmission Systems D.S. McPherson, F. Pera, M. Tazlauanu, S.P. Voinigescu Quake.
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation.
ECE 333 Linear Electronics
Lab 3 MOSFET Capacitance
Chapter 3 Fabrication, Layout, and Simulation.
Modeling Rp B R1 CL A R2 Cint
3. Advanced Rules & Models
Multiple Drain Transistor-Based FPGA Architectures
CMOS Modeling Services from AdMOS
An Illustration of 0.1µm CMOS layout design on PC
INTRODUCING MICROWIND
Fig. 2 Materials and designs for bioresorbable PC microcavity-based pressure and temperature sensors. Materials and designs for bioresorbable PC microcavity-based.
Fig. 4 Short-channel 2L-OFET for cutoff frequency measurement.
Presentation transcript:

IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Modelling of RF LDMOS Transistors Using BSIM3 B. Senapati, K. Ehwald, I. Shevchenko, V. Dykyy, and F. Fürnhammer

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Outline LDMOS device cross-section of LDMOS LDMOS model SPICE sub-circuit model for LDMOS using bsim3v3 JFET to model the pinch-off the drift-region Measurements and extraction setup for RF and DC measurements extraction tool Results DC results and RF results Conclusion

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved LDMOS Device Structure LDMOS is fabricated into an advanced industrial 0.25µm BiCMOS process. Source and substrate are common together to reduce the source resistance and inductance Length of the drift region is 1  m Gate length, width and finger number are 0.28  m, 5.6  m and 10, respectively K.-E. Ehwald et al., High Performance RF LDMOS Transistors with 5nm Gate Oxide in 0.25µm SiGe:C BiCMOS Technology, IEDM Tech. Dig, 2001

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved SPICE Sub-circuit Model of LDMOS BSIM3v3 model for the intrinsic MOS JFET model for the drift-region AD, AS, PD and PS of BSIM3 are zero

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Measurement Setup DC-measurements (4142B) using Kelvin probes CV measurements (4284A) RF measurements (PNA E8364A) 45 MHz - 50 GHz Temperature range -40 °C °C Software IC-CAP (version 2002)

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved DC and CV Results

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved RF Results

IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Conclusion LDMOS large signal model has been developed using BSIM3v3 JFET used to model the pich-off of the drift region Model includes dc including qusi-saturation, non- standerd capaciatce and high frequency Model has been verified by comparing simulation with measurement More accurate physical model required for modeling the drift region On-going work is in the Self-heating and temperature modelling