Implementation of a noise subtraction algorithm using Verilog HDL University of Massachusetts, Amherst Department of Electrical & Computer Engineering, Course 559/659 by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas Kunkel Team Leader: Prof. Maciej Ciesielski

Noise-subtracting algorithm " Time to frequency transformation " Subtraction of magnitudes " Distortion correction " Frequency to time transformation Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm " Serial data " Shifts of 16bits " Storing in 1032 x 32bit memory " Flushing memory to FFT after receiving of 256 pairs of data Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm State machine storing data in memory Flushing memory Buffering data Emptying buffer Reset256 pairs Mem flushed Buffer emptied Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm Block Diagram Data SCLK LRCLK ResetData Address WR RD Flushing EnableDone Hold Data Real part Imaginary Valid Output Serial shifter 16bit counter Address generator Buffer Finite state machine 1024 x 32bit RAM Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm " Parallel input and output of variables " 16Bit address, 8Bit data (compatible to microcontroller) " Preset values when resetting Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm " Implementation of Radix 2 algorithm " Window length 1024 " 16Bit fixed point arithmetics " 2 FFTs at the same time by using real and imaginary signal " Reconstruction afterwards needed Algorithm Modules FFT Subtraction In- / Output

+ + WkWk A B C D - x Noise-subtracting algorithm " Butterfly structure as fundamental cell Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm W0W0 W0W0 W2W2 W2W2 W3W3 W0W0 W2W2 W1W1 f(0) f(7) F(0) F(1) F(2) F(3) F(4) F(5) F(6) F(7) Signal-flow Graph for 8 point FFT Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm " Sequential implementation " 1Bit shiftdown after each step to prevent overflow " RAM 1024 x 32Bit " Controller (Finite state machine) " Address generator " Coefficient ROM Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm ram_addr1 Controller Address Generator RAM Butterfly Processor Coeff. ROM rom_addr ram_addr2 twiddle write_en read_en Data Bus io_mode fft_mode input_mode fft_doneio_done bus_select Data In Data Out input_readyoutput_ready FFT PROCESSOR Block Diagram Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm Delay estimation Input: 512 FFT processing:2*512*10 output:512 Sum clock cycles Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm Simulations Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm Spectra reconstruction Re Im Re Im Re Im Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm Error compared to 32bit floating point Absolute Error Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm Error compared to 32bit floating point Algorithm Modules FFT Subtraction In- / Output

(absolute values plotted) Noise-subtracting algorithm Error compared to 32bit floating point Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm 16 Alpha Beta Sub Comp a sel b 1 if x>y, else 0 x Block diagram Algorithm Modules FFT Subtraction In- / Output

Noise-subtracting algorithm Inputs: two, 16 unsigned bits each ( A and B) Multiplication: Alpha and Beta terms Subtraction: ((original A)-(Alpha*B)) Comparators: (A > B) out =1, else out =0 Multiplexer: (Inputs: Select, A*Beta, subtractor output) Select = 1, final_out = x Select = 0, final_out = y Algorithm Modules FFT Subtraction In- / Output