הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות Final Presentation Fast Ethernet Card with FPGA Fast Ethernet Card with FPGA Project num Students: Alex Shpiner Eyal Azran Supervisor: Boaz Mizrahi

Features Transmitting and Receiving Ethernet frames Transmitting and Receiving Ethernet frames MAC and PHY configuration control MAC and PHY configuration control Driver Software for controlling card interface Driver Software for controlling card interface Full control by the driver of the MAC features: Full control by the driver of the MAC features:  Full/Half Duplex  10/100 Mb/sec  MAC address configuration  64 bit Multicast Filter

The work flow Time line VHDL studying Developing the algorithms Synthesis & Debug Writing the code Simulations March to April 2003 May 2003 June to August 2003 Sep. to Oct November 2003

View from the top FPGA PLXPLX MACMAC PHYPHY PCIPCI ETHERNETETHERNET - Data Flow - Control Signals

PCIBRIDGEPCIBRIDGE MACMAC PHY CIFCIF GNR MCF TRN RCV ARB FPGA block diagram Shared bus

CIF – CPU Interface Unit CIF PLXPLX Passing information (data, control signals) from PLX to all other entities. Decode the address given from PLX and passing the data to the addressed unit.

Configuration Units GNR – General Configurations Configures MAC and PHY’s pins MCF – MAC Configuration Configures MAC's Internal configuration registers GNR MCF CIFCIF MAC PHY

Transmitting and Receiving TRN RCV ARB TRN – Transmitting unit RCV – Receiving unit The arbitration algorithm will be overviewed in the next slides CIFCIF MACMAC

Testing Units CIF TRN RCV PLX MACMAC PCTCITTRT Used during debugging Checks the correctness of the protocols. Filling the internal register upon signals on checked bus. Internal registers are read through CIF. Have addresses on memory map.

The arbitration module – The Problem I want to send mail to my boyfriend!

I want to download the latest exercise in HEDVA!! I want to send mail to my boyfriend! The arbitration module – The Problem

I want to download the latest exercise in HEDVA!! Problem - there is only one bus from FPGA to MAC! I want to send mail to my boyfriend! The arbitration module – The Problem

The arbitration module – The Solution ARB TRN RCV request done grant done request grant  Algorithm is based on Preemptive Round Robin  Differential quantum  Early finish option  RCV has higher priority

Design considerations

 TRN quantum

Design considerations  TRN quantum  RCV quantum

Design considerations  TRN quantum  RCV quantum  TRN FIFO size

Design considerations  TRN quantum  RCV quantum  TRN FIFO size  RCV FIFO size

Design considerations  TRN quantum  RCV quantum  TRN FIFO size  RCV FIFO size All calculations can be found in the project book.

Future versions may include… Frame processing

Future versions may include… Frame processing Decoding

Future versions may include… Frame processing Decoding Encryption

Future versions may include… Frame processing Decoding Encryption Compression

Future versions may include… Frame processing Decoding Encryption Compression Ping reply in hardware

Future versions may include… Frame processing Decoding Encryption Compression Ping reply in hardware Frames filter in hardware

Future versions may include… Frame processing Decoding Encryption Compression Ping reply in hardware Frames filter in hardware And so on…

Thanks… Boaz Mizrachi Eli Shoshan Michael Itzkovitz Moni Orbach Ina Rivkin Broria Zohar Anat Gavish Tomer Schatzberger Yaron Dror Gabi Zafrir Gidi Boris Kostya Dmitry And all the stuff and students of the dig lab