טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Midterm Presentation Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004 Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004

Memory Controller for Satellite Problems In Space Short time “ Bit Flips ” Permanent malfunction – “ Latch Ups ” Memory is especially vulnerable to these kind of failures !

Memory Controller for Satellite Block Diagram of Conventional Memory System PowerPC405 ( CPU ) SDRAM Memory PLB Memory Controller

Memory Controller for Satellite Block Diagram of a Memory System using TMR with 3 Conventional Controllers PowerPC405 ( CPU ) SDRAM Memory PLB Memory Controller 1 SDRAM Memory Controller 2 Memory Controller 3 TMR Unit SDRAM Memory EDAC

Memory Controller for Satellite Basic System Information Operating frequency : 100 MHz Max BW : 400 MB/Sec (or 133 MB/sec due to hardware constraints). Refresh cycle: 64msec 32 bits of data bus 32 bits of address.

Memory Controller for Satellite Read PLB Transaction

Memory Controller for Satellite Write PLB Transaction

Memory Controller for Satellite SDRAM Block Diagram

Memory Controller for Satellite 8M X 16 SDRAM

Memory Controller for Satellite SDRAM Read Transaction

Memory Controller for Satellite SDRAM Write Transaction

Memory Controller for Satellite Block Diagram of a Memory System with Corruption Unit PowerPC405 ( CPU ) SDRAM Memory SDRAM Memory SDRAM Memory Controller PLB EDAC Corruption Unit

Memory Controller for Satellite Completed Tasks Study the Virtex-II Pro component design. Study the PPC405 Processor core Study the VHDL development environment and VHDL. Writing a tester hardware of the LED ’ s – from VHDL design through synthesis, and place&route using Xillinx EDK. Midterm

Memory Controller for Satellite First Semester Goals Writing a tester software for the Power PC (activation of LCD). Writing a tester software with use of UART capabilities (Telnet). Building up a standard computer system and writing an application to test its memory. Implementing an hardware which corrupts the memory. First draft of a reliable memory system. Final

Memory Controller for Satellite Second Semester Goals Study the probability model of error in a memory system in space. Review different options of possible memory controllers and EDAC in means of optimal BER. Implementation of the optimal (if possible) memory controller and EDAC unit. Debug. System integration of the memory system in a complete computer system.