Power Aware Solutions for NoC Architecture Yaniv Ben-Itzhak Noc Seminar Winter 08.

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Presentation transcript:

Power Aware Solutions for NoC Architecture Yaniv Ben-Itzhak Noc Seminar Winter 08

Power Aware Various Solutions SoC Mapping blocks. Routing. Scheduling. CMP (MPSoC) Threads Allocation. Routing. Scheduling.

Power Aware Various Solutions SoC Mapping blocks. Routing. Scheduling. CMP (MPSoC) Threads Allocation. Routing. Scheduling.

SoC Radu Marculescu & Jingcao Hu: Exploiting the Routing Flexibility for Energy Performance Aware Mapping of Regular NoC Architectures (2003) Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time (2004) Energy-and Performance-Aware Mapping for Regular NoC Architectures (2005) Communication and Task Scheduling of Application-Specific Networks-on- Chip (2005)

Problem Formulation How to map each IP to which tile ? Total communication energy consumption is minimized

Communication Energy Model Energy consumed by the switch Energy consumed on the links Energy consumed by the buffer Energy consumed by the internal wires negligible

Communication Energy Model Energy consumed by the switch Energy consumed on the links

Communication Energy Model Energy consumed by the switch Energy consumed on the links Calculated independently of the underlying traffic model. Determined by the Manhattan distance between them.

Solution Application Characterization Graph (APCG) G = G(C,A) : c i represents one selected IP. a i, j characterizes the communication from c i to c j. v(a i, j ): communication volume (bits) from c i to c j. b(a i, j ): arc minimum bandwidth requirement from vertex c i to c j,

Solution Architecture Characterization Graph (ARCG) G =G(T,R): t i represents one tile in the architecture. r i, j represents the routing from t i to t j: P i, j : a set of candidate minimal paths from tile t i to tile t j. e(r i, j ):

Solution Find mapping function map() from APCG to ARCG and a deadlock-free, minimal routing function, which: communication volume (bits) from c i to c j

Solution The search space of the problem increases factorially with the system size. For System with 4X4 tiles, there are 16! Possible mappings !!

Solution Branch-and-Bound Algorithm

Power Aware Various Solutions SoC Mapping blocks. Routing. Scheduling. CMP Threads Allocation. Routing. Scheduling.

1 CMP (MPSoC( Threads Allocation Nero PhotoShop WinRar Quake 4 Threads Allocation

Nero PhotoShop WinRar Quake 4 Off CMP (MPSoC( Threads Allocation

CMP (MPSoC( Basic Processor Model Cache Miss T(p) Idle t(p) p Cache Miss …

CMP (MPSoC( Basic Processor Model Power = Power processors + Power NoC

CMP (MPSoC( Basic Processor Model Power = Power processors + Power NoC Power NoC calculated by bit energy model Depends on the Architecture (Cache in the Middle,Tiled CMP, Message Passing)

CMP (MPSoC( Basic Processor Model Threads Total Average Performance (All processors)

CMP (MPSoC( Power = Power processors + Power NoC P NoC calculated by bit energy model

CMP (MPSoC( Avg. Performance Threads Performance Average

CMP (MPSoC( Threads Allocation with constraints of: Asymmetry. Shared Memory –  Cache in the Middle  Tiled CMP Architecture. Message Passing. Threads Allocation with: Processors On/Off. DVS - Dynamic Voltage Scaling. DFS - Dynamic Frequency Scaling.

Questions ? Thank You !