Embedded System Programming Programming DIO on the Puppeteer.

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Embedded System Programming Programming DIO on the Puppeteer

SA1110 Memory Map

FPGA DIO Register locations RegisterAddress FPGA_6K_BASE0x FPGA_6K_DIO_REG_BASE0x FPGA_6K_DIO_DATA_REG0x FPGA_6K_DIO_DIR_REG0x FPGA_6K_DIO1_REG_BASE0x FPGA_6K_DIO1_DATA_REG0x FPGA_6K_DIO1_DIR_REG0x FPGA_6K_DIO2_REG_BASE0x FPGA_6K_DIO2_DATA_REG0x FPGA_6K_DIO1_DIR_REG0x104006A8 OB_LED_ADDRESS0x

SA1110, FLEX 6K and CPLD SA1110 StrongARM Altera FLEX 6k FPGA CPLD Board GPIO and Data Lines

Address-Register-Port mappings LEDs can be used for diagnostics The top bits of port C are latches 0x x Port B Port A Port C On board LEDS FPGA_6K_DIO1 bits FPGA_6K_DIO1 bits FPGA_6K_DIO2 bits OB_LED_ADDRESS bits

Port layout Port BOutputs to LEDS Port AInputs from switches Port COutputs to motor This assignment is just for the application board For other application areas we would require other configurations

Port C latches These bit are used to latch the data to the particular port For changes such as to the data direction register a high/low transition is required It is also used for outputting onto pins Not necessary for reading inputs BitLatches 6Port C 7Port B 8Port A

#include #define DRIVER_AUTHOR "craig duffy #define DRIVER_DESC "FPGA DIO driver" #define LED_ADDRESS 0xf #define RGGG 0xf000 static int fpga_dio_init(void) { static int fpga_j; static short unsigned pattern; printk(KERN_ALERT "fpga dio loaded\n"); pattern=RGGG; pattern = pattern >> 4; for ( fpga_j=0; fpga_j != 16 ; fpga_j++) { printk("pattern %x\n",pattern); udelay(400); writew(pattern,LED_ADDRESS); pattern = pattern >> 8; pattern--; pattern = pattern << 8; }*/ return 0; } static void fpga_dio_exit(void) { printk(KERN_ALERT "fpga dio unloaded\n"); } module_init(fpga_dio_init); module_exit(fpga_dio_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_SUPPORTED_DEVICE("fpga_dio");

Makefile for building loadable modules You will probably have to change the INCLUDE path for your kernel’s includes. #makefile for loadable modules. 2.4.N kernels TARGET:= fpga_dio WARN:= -W -Wall -Wstrict-prototypes -Wmissing-prototypes -fvolatile -mshort-load-words INCLUDE:= -isystem /usr/local/src/linux/include CFLAGS:= -O2 -DMODULE -D__KERNEL__ -mtune=strongarm -march=armv4 ${WARN} ${INCLUDE} ASFLAGS := -fverbose-asm -S CC:= arm-linux-gcc ${TARGET}.o : ${TARGET}.c.PHONY: clean clean: rm -rf ${TARGET}.o Module makefile

/******************************************************************************/ /* */ /* DIOGetInputs() */ /* */ /******************************************************************************/ u8 DIOGetInputs(unsigned u32Bank, unsigned int* pu32Result) { static u8 RetVal = 1; /* Initialise to success */ static volatile unsigned short * p6KDIODataReg; static unsigned short u16InputReg; /************************************************************/ /* */ /* Set the data register. */ /* */ /************************************************************/ switch(u32Bank) { case 0: p6KDIODataReg = (volatile unsigned short*) FPGA_6K_DIO_INPUT_REG; break; case 1: p6KDIODataReg = (volatile unsigned short*) FPGA_6K_DIO1_DATA_REG; break; case 2: p6KDIODataReg = (volatile unsigned short*) FPGA_6K_DIO2_DATA_REG; break; case 3: // COM1 handshake lines p6KDIODataReg = (volatile unsigned short*) (FPGA_6K_BASE + 0x300); break; case 4: // COM2 handshake lines p6KDIODataReg = (volatile unsigned short*) (FPGA_6K_BASE + 0x380); break; } /************************************************************/ /* */ /* Read the data register. */ /* */ /************************************************************/ u16InputReg = *p6KDIODataReg; if (pu32Result) *pu32Result = (unsigned int) u16InputReg; else RetVal = 0; return RetVal; } /* DIOGetInputs */

/******************************************************************************/ /* */ /* DIOSetDirection() */ /* */ /******************************************************************************/ unsigned short DIOSetDirection(unsigned int u32Bank, unsigned int u32Mask, unsigned int u32Data) { static unsigned short OldRegVal; /* save and return old register value */ static volatile unsigned short* p6KDIODirReg; static unsigned short u16DirReg; /************************************************************/ /* */ /* Set the direction register and its shadow. */ /* */ /************************************************************/ switch(u32Bank) { case 0: p6KDIODirReg = (volatile unsigned short*) FPGA_6K_DIO_DIR_REG; break; case 1: p6KDIODirReg = (volatile unsigned short*) FPGA_6K_DIO1_DIR_REG; break; case 2: p6KDIODirReg = (volatile unsigned short*) FPGA_6K_DIO2_DIR_REG; break; } /************************************************************/ /* */ /* Set the direction register. */ /* */ /************************************************************/ u16DirReg = *p6KDIODirReg; OldRegVal = u16DirReg; u16DirReg &= (unsigned short) (~u32Mask); u16DirReg |= (unsigned short) (u32Mask & u32Data); *p6KDIODirReg = u16DirReg; u16DirReg = *p6KDIODirReg; return OldRegVal; } /* DIOSetDirection */

/******************************************************************************/ /* */ /* DIOSetOutputs() */ /* */ /******************************************************************************/ unsigned short DIOSetOutputs(unsigned int u32Bank, unsigned int u32Mask, unsigned int u32Data) { static unsigned short OldRegVal; /*return old register value */ volatile unsigned short* p6KDIODataReg; static unsigned short u16OutputReg; /************************************************************/ /* */ /* Set the data register. */ /* */ /************************************************************/ switch(u32Bank) { case 0: p6KDIODataReg = (volatile unsigned short*) FPGA_6K_DIO_OUTPUT_REG; break; case 1: p6KDIODataReg = (volatile unsigned short*) FPGA_6K_DIO1_DATA_REG; break; case 2: p6KDIODataReg = (volatile unsigned short*) FPGA_6K_DIO2_DATA_REG; break; case 3: // COM1 handshake lines p6KDIODataReg = (volatile unsigned short*) (FPGA_6K_BASE + 0x300); break; case 4: // COM2 handshake lines p6KDIODataReg = (volatile unsigned short*) (FPGA_6K_BASE + 0x380); break; } /************************************************************/ /* */ /* Read and update the data register. */ /* */ /************************************************************/ u16OutputReg = *p6KDIODataReg; OldRegVal = u16OutputReg; u16OutputReg &= (unsigned short) (~u32Mask); u16OutputReg |= (unsigned short) (u32Mask & u32Data); *p6KDIODataReg = u16OutputReg; u16OutputReg = *p6KDIODataReg; return OldRegVal; } /* DIOSetOutputs */