HTR status Tullio Grassi Univ. of Maryland Feb 2004

Rev4 board From TB2003 and following test, most of the timing issues were associated to external/temporary clock modules. Major changes dictated by the SLB: 1) HTR system clock will be from the local TTCrx, not the special clock distributed by the Fanout card. 2) Power sequence for SLB Other minor changes and including: - keyed connectors on the front-panel - user-friendly (keyed connector, eliminate clock/power sequence, etc) - optimized critical clock and data lines

HTR Rev4 status Last week received 3 boards Debugging: no big issues so far We could send 1 or 2 boards to US institutions We are receiving the first SLB: major tests Need to find a Cern-approved cable to DCC

Need to define and “enforce” overall procedures For MTP ribbons Handy, safe Ok for dust Not for oily dirt HTR optical receivers: There are procedures that we have not followed. Cleaning issues

Trigger cable “Baseline” skew-clear cable Tested by ECAL: OK Cat6 tested in UMD : We measured it with the Wisconsin test kit:  ,

Test boards FE-emulator: delivered one box to Cern, more being stuffed. Trigger link receiver: still under design, we got complete documentation from Wisconsin in January

Error Reporting/Recovery Monitoring paths: HTR  DCC  CMS Trigger Control System VME: alarming system, spy, slow monitoring What need to be monitored: FE status (with CapIDs) FE-link (flag bits, FE/HTR data format) TTCrx READY Xilinx DLL Actions: reset Trigger Primitives send errors to DCC DCC will hold 1 orbit’s worth of data, wait for orbit veto…under discussion Studying a scheme to monitor these

TPG alignment – BCID idea Baseline scheme: histogram the LHC beam structure. In principle this procedure corrects any source of data mis-alignment. Ch N Ch N+1 Ch N+2 Global BC0 Delay individually each channel and align it to the global BC0 NB: this scheme was conceived for the trigger-path, but now we plan to use it also in the DAQ-path.

TPG alignment – BCID implementation Unique board for HCAL and possibly ECAL HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR … … Rack-to-Rack CAT 7 Low-skew distribution tree for global BC0 (and CLK) VME : get histograms results and adjust timing Fanout Card (in GLOBAL mode) Fanout Card (in CRATE mode) Fanout Card (in CRATE mode) Fanout Card (in CRATE mode) One board per crate

TPG alignment – BCID problem In principle the procedure should be repeated every time an optical link is lost and re-established. We want : mean-time-between-loss-of-link >> histogramming-time Shuichi and Salavat are studying how long it takes to distinguish the signal from the noise. RESULTS ? Problem for HO (low-luminosity; DAQ-path only) ?

Backup scheme for alignment An alternative scheme is awkward, as it would require to: study the latency of TTC fibers to FE calibrate all TTCrx (including in the FE) send the orbit message with FE_BC0 rely on all fibers having the same length As a complement of the histogram scheme, the orbit message could be useful if a few links drop after the histogram procedure.

L1A Trigger Synchronization L1A Trigger from each TTCrx has a different latency (~20 ns). Need a calibration procedure for each TTCrx in the HTR. This is should be done in-situ (USC55) Using LED pulses ?

Subsystem Software Plans Code developed from having to: –Debug at US contributing institutions Code to do VME operations to talk to HTR will be integrated –For debugging –For for production checkout –Run at H2 XDAQ, DCS, etc. under development –Vertical slice At this time…primitive, but effective

Return Air Guide Power Supply Zone Fan Tray Air/Water Heat Exchanger Cable Strain Relief Fan Tray Air/Water Heat Exchanger VME Rack Layout –Optical patch panel (192 LC fibers) –Recirculation Fan and Monitoring –Extra Heat Exchanger –2 VME crate zones: Cable support (panel only) –Which Trigger cables? 9U Crate (1.5kW) Air/Water heat exchanger Fan Tray –Power Supply: does it exist ? 3-phase power and remote shutoff Vertical air flow Put A/C circuit breakers here? Add ~33% power dissipation –Return air guide with Smoke Detector? (2U) 6U Cable Strain Relief Air/Water Heat Exchanger Turbine / Rack Protection HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR DCCDCC DCCDCC CLKCLK SBSSBS HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR HTRHTR DCCDCC DCCDCC CLKCLK SBSSBS 2U 9U 4U 2U 9U 4U 2U 4U 56U CONSTRAINTS height  56U closed-loop air circulation dissipation  10kW 3-phase power-supplies Rack computer on a separate rack Optical patch panel 4U

Schedule HTR-SLB-RCT connectivity & clock Histogram procedure; firmware for summing TB2004 & Slice test Production Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2 Test in the Electronics Integration Centre Install in USC55 (integr. with FE; ECAL) Integrate with RCT, DAQ Receive real Triggers

Appendix: Detailed Schedule Dec03-Mar04 : Verify that HTR and SLB talk to each other; run Trigger Link with QPLL and Wisconsin's kit; Cables studies (no histogramming, no LHC structure) Apr-Dec04: - Test UMD Regional-Cal-Trigger (RCT) Emulator board (Winsconsin Receive mezzanine + FPGA capabilities). - Emulate LHC structure with FE emulator and use histogramming feature of SLB - Software/firmware development to use the SLB to fix the random latency in the DAQ-path - Firmware for all summing cases in Trigger-Path (effort depends on target latency) May-Sep 04: TB Production cards or TB2003 cards, first day of beam is priority - No trigger primitive output May-Dec 04: Vertical Slice Operations, SX5 - Rev4 production cards prioritized over starting day - trigger link BER, no LHC structure. Jan-Jun05: Testing in the surface Electronics Integration Centre - Required by the Commissioning Task Force (P. Sharp) - Common facilities, reduce problems - several FE-emulators with LHC structure (or FE-cards ?), histogramming in SLB, RCT-emulator - test crate-to-crate synchronization of Trigger Primitives. - test re-alignement in the DAQ-path with timing from SLB - start test and calibration of L1A from all HTR TTCrx Jun-Dec05: Install/Commission HCAL crates in USC55 - Integration with HCAL FE - Integration of TPGs with ECAL readout (validate clock distribution tree) ? Dec05-Jun06: Integrate with Regional Trigger, DAQ Jun-Nov06: Receive Trigger from Global Trigger System

Appendix: TTCrx latency Date: Fri, 23 Jan :16: From: Paulo Rodrigues Simoes Moreira To: Hello Tulio The latency is in fact not random but, it will vary from chip to chip. On purpose we didn't specify any value because we think the user should not rely on this. Almost all the systems using the TTCrx will require calibration so the absolute delay is not important. Additionally delays will also depend on the pin receiver, fibre and laser transmitter as well as temperature power supply voltage and optical power. For the same chips the latency will be fixed for all the clock signals and trigger signals. There will be of course a dependence with power supply voltage and temperature.

Appendix: Issue on the rack layout 1) Does the “Recirculation Fan/Rack Protection” module correspond to the turbine described on: Then it should be only 3U, not 4U [see also 2.1 of: ] 2) Does the “Return air guide” module includes the smoke detector and air deflector, described on the same page: This module is 3U on Figure 4 of: ] 3) Does the rack include front panels in order to close the crates as in: 5) It seems that there are power supply that let the air flow vertically [see of the “TECHNICAL SPECIFICATION FOR SUBRACKS FOR LHC EXPERIMENTS”]. What’s their power dissipation (add 33% as on 2.3 of ) ?