Digilab 7-Segment Displays Lab 4

selyInstruction name “000”true if b = a false otherwise = “001”true if b /= a false otherwise <> “010”true if b < a (unsigned) false otherwise U< “011”true if b > a (unsigned) false otherwise U> “100”true if b <= a (unsigned) false otherwise U<= “101”true if b < a (signed) false otherwise < “110”true if b > a (signed) false otherwise > “111”true if b <= a (signed) false otherwise <=

Digilab2 – DIO1 Boards Four 7-segment displays dig1dig2dig3dig4

Digilab2 Board – Common Anodes A1 A2 A3 A4 AtoG(6 downto 0) Pins

switches 7-segment displays LEDs pushbuttons Digilab XLA

Digilab Board dig3dig2dig1dig4

Digilab XLA Board – Common Anodes A4 A3 A2 A1 CA CB CC CD CE CF CG Pins

7-Segment Decoder a-g LOW to turn on segment

library IEEE; use IEEE.std_logic_1164.all; entity seg7dec is port (q: in STD_LOGIC_VECTOR(3 downto 0); AtoG: out STD_LOGIC_VECTOR(6 downto 0)); end seg7dec; 7-Segment Decoder

architecture seg7dec_arch of seg7dec is begin process(q) begin case q is when "0000" => AtoG <= " "; when "0001" => AtoG <= " "; when "0010" => AtoG <= " "; when "0011" => AtoG <= " "; when "0100" => AtoG <= " "; when "0101" => AtoG <= " "; when "0110" => AtoG <= " "; when "0111" => AtoG <= " "; when "1000" => AtoG <= " "; when "1001" => AtoG <= " "; when "1010" => AtoG <= " "; when "1011" => AtoG <= " "; when "1100" => AtoG <= " "; when "1101" => AtoG <= " "; when "1110" => AtoG <= " "; when others => AtoG <= " "; end case; end process; end seg7dec_arch;

Digilab2 Board – Common Anodes A1 A2 A3 A4 AtoG(6 downto 0) Pins

Multiplex displays

Multiplex displays

Multiplex displays

Multiplex displays

Lab 4

signal clkdiv: std_logic_vector(23 downto 0); begin -- Divide the master clock (50MHz) down -- to a lower frequency. process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; cclk <= clkdiv(17); Hz = 50MHz/2^18

-- A 2-bit up-counter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ctr2bit is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (1 downto 0) ); end ctr2bit; ctr2bit.vhd

architecture ctr2bit_arch of ctr2bit is begin process (clk, clr) variable COUNT: STD_LOGIC_VECTOR (1 downto 0); begin if clr = '1' then q <= "00"; elsif clk'event and clk='1' then COUNT := COUNT + 1; q <= COUNT; end if; end process; end ctr2bit_arch; ctr2bit.vhd

Lab 4

library IEEE; use IEEE.std_logic_1164.all; entity Acode is port ( Aen: in STD_LOGIC_VECTOR (3 downto 0); Asel: in STD_LOGIC_VECTOR (1 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) ); end Acode; Acode.vhd

architecture Acode_arch of Acode is begin process(Aen, Asel) begin A <= "0000"; case Asel is when "00" => if Aen(1) = '1' then A <= "1000"; end if; when "01" => if Aen(2) = '1' then A <= "0100"; end if; when "10" => if Aen(3) = '1' then A <= "0010"; end if; when others => if Aen(4) = '1' then A <= "0001"; end if; end case; end process; end Acode_arch; Acode.vhd

Lab 4

-- System Library Components component IBUFG port ( I : in STD_LOGIC; O : out std_logic ); end component; U00:IBUFG port map (I => bn, O => bnbuf);