11/15/2004EE 42 fall 2004 lecture 321 Lecture #32 Registers, counters etc. Last lecture: –Digital circuits with feedback –Clocks –Flip-Flops This Lecture: –Edge triggers –Registers –shift registers –counters

11/15/2004EE 42 fall 2004 lecture 322 Edge triggering The last lecture ended with how a flip flop could be designed by using two latches which cascaded in a master-slave relationship. Another way of creating an edge triggered flip flop is to use logic with feedback, as in the following slide.

11/15/2004EE 42 fall 2004 lecture 323 Q D Clk=1 R S Q’ negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input characteristic equation Q(t+1) = D holds D' when clock goes low holds D when clock goes low Edge-Triggered Flip-Flops More efficient solution: only 6 gates –sensitive to inputs only near edge of clock signal (not while high)

11/15/2004EE 42 fall 2004 lecture 324 positive edge-triggered FF negative edge-triggered FF D CLK Q pos Q pos' Q neg Q neg' 100 Edge-Triggered Flip-Flops (cont’d) Positive edge-triggered –Inputs sampled on rising edge; outputs change after rising edge Negative edge-triggered flip-flops –Inputs sampled on falling edge; outputs change after falling edge

11/15/2004EE 42 fall 2004 lecture 325 Timing Methodologies As we have seen, there are several different ways of designing a sequential logic circuit. In general, each circuit will stick with a set of rules which are designed to achieve consistently accurate results. A set of rules for interconnecting components and clocks are adopted which will guarantee proper operation of system when strictly followed. Approach depends on building blocks used for memory elements. Edge-triggered flip-flops are found in programmable logic devices Many custom integrated circuits focus on level- sensitive latches

11/15/2004EE 42 fall 2004 lecture 326 Basic rules for correct timing: –Inputs to flip-flops are stable and correct for and interval around the time of sampling (avoid asynchronous inputs wherever possible) –No flip-flop changes state more than once per clocking event

11/15/2004EE 42 fall 2004 lecture 327 clock data changingstable input clock T su ThTh clock data DQDQ Definition: Set up time/hold time To ensure that the data signal is captured accurately, the data must be stable for an time t su (set up) before the edge, and kept constant for a time t h (hold) after the edge.

11/15/2004EE 42 fall 2004 lecture 328 behavior is the same unless input changes while the clock is high DQDQ CLK positive edge-triggered flip-flop DQDQ G CLK transparent (level-sensitive) latch D CLK Q edge Q latch Comparison of Latches and Flip-Flops

11/15/2004EE 42 fall 2004 lecture 329 TypeWhen inputs are sampledWhen output is valid unclockedalwayspropagation delay from input change latch level-sensitiveclock highpropagation delay from input change latch(T su /T h around fallingor clock edge (whichever is later) edge of clock) master-slaveclock highpropagation delay from falling edge flip-flop(T su /T h around fallingof clock edge of clock) negativeclock hi-to-lo transitionpropagation delay from falling edge edge-triggered(T su /T h around fallingof clock flip-flopedge of clock) Comparison of Latches and Flip-Flops (cont’d)

11/15/2004EE 42 fall 2004 lecture 3210 all measurements are made from the clocking event that is, the rising edge of the clock Typical Timing Specifications Positive edge-triggered D flip-flop –Setup and hold times –Minimum clock width –Propagation delays T h 0.5 ns T w 1ns T su 0.8 ns D CLK T su 0.8 ns T h 0.5 ns

11/15/2004EE 42 fall 2004 lecture 3211 IN Q0 Q1 CLK 100 Cascading Edge-triggered Flip-Flops Shift register –New value goes into first stage –While previous value of first stage goes into second stage –The propagation time must be longer than the hold time CLK IN Q0Q1 DQDQOUT

11/15/2004EE 42 fall 2004 lecture 3212 timing constraints guarantee proper operation of cascaded components assumes infinitely fast distribution of the clock Cascading Edge-triggered Flip- Flops (cont’d) Why this works –Propagation delays exceed hold times –Clock width constraint exceeds setup time –This guarantees following stage will latch current value before it changes to new value T su 4ns T p 3ns T h 2ns In Q0 Q1 CLK T su 4ns T p 3ns T h 2ns

11/15/2004EE 42 fall 2004 lecture 3213 original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1 CLK1 is a delayed version of CLK0 In Q0 Q1 CLK0 CLK1 100 Clock Skew The problem –Correct behavior assumes next state of all storage elements determined by all storage elements at the same time –This is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic –Effect of skew on cascaded flip-flops:

11/15/2004EE 42 fall 2004 lecture 3214 Summary of Latches and Flip- Flops Development of D-Flip-Flop –Level-sensitive used in custom integrated circuits can be made with 4 gates –Edge-triggered used in programmable logic devices –Good choice for data storage register Historically J-K Flip Flop was popular but now never used –Similar to R-S but with 1-1 being used to toggle output (complement state) –Can always be implemented using D-FF Preset and clear inputs are highly desirable on flip-flops –Used at start-up or to reset system to a known state

11/15/2004EE 42 fall 2004 lecture 3215 Flip-Flop Features Reset (set state to 0) – R –Synchronous: D new = R' D old (when next clock edge arrives) –Asynchronous: doesn't wait for clock, quick but dangerous Preset or set (set state to 1) – S (or sometimes P) –Synchronous: D new = D old + S (when next clock edge arrives) –Asynchronous: doesn't wait for clock, quick but dangerous Both reset and preset –D new = R' D old + S (set-dominant) –D new = R' D old + R'S(reset-dominant) Selective input capability (input enable/load) – LD or EN –Multiplexer at input: D new = LD' Q + LD D old –Load may/may not override reset/set (usually R/S have priority) Complementary outputs – Q and Q'

11/15/2004EE 42 fall 2004 lecture 3216 RSRSRS DQDQDQDQ OUT1OUT2OUT3OUT4 CLK IN1IN2IN3IN4 RS "0" Registers Collections of flip-flops with similar controls and logic –Stored values somehow related (e.g., form binary value) –Share clock, reset, and set lines –Similar logic at each stage Examples –Shift registers –Counters

11/15/2004EE 42 fall 2004 lecture 3217 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK Shift Register Holds samples of input –Store last 4 input values in sequence –4-bit shift register:

11/15/2004EE 42 fall 2004 lecture 3218 parallel inputs parallel outputs serial transmission Shift Register Application Parallel-to-serial conversion for serial transmission

11/15/2004EE 42 fall 2004 lecture 3219 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK OUT Pattern Recognizer Combinational function of input samples –In this case, recognizing the pattern 1001 on the single input signal

11/15/2004EE 42 fall 2004 lecture 3220 Binary Counter Logic between registers (not just multiplexer) –XOR decides when bit should be toggled –Always for low-order bit, only when first bit is true for second bit, and so on

11/15/2004EE 42 fall 2004 lecture 3221 Sequential Logic Summary Fundamental building block of circuits with state –R-S latch, R-S master/slave, D master/slave, edge-triggered D FF –Latch and flip-flop Timing methodologies –Use of clocks –Cascaded FFs work because prop delays exceed hold times –Beware of clock skew Asynchronous inputs and their dangers –Synchronizer failure: what it is and how to minimize its impact Basic registers –Shift registers –Pattern detectors –Counters