CISC and RISC L1 Prof. Sin-Min Lee Department of Mathematics and Computer Science

We shall define a RISC as a computer that has most of the following properties Instructions are conceptually simple Instructions are of a uniform length Instructions use one (or very few) instruction formats The instruction set is orthogonal Instructions use one or very few addressing modes The architecture is a load-and-store architecture The architecture supports two or a few more datatypes

Major techniques used to implement RISC computers: RISC s use pipelining to speed up instruction decoding and execution (thus RISC s have separate functional units) RISC s usually do not allow program self-modification RISC s use Harvard architectures (separate instruction stream and bus stream) RISC s use large register set to reduce CPU-to-memory traffic RISC s often use delayed branches to avoid branch penalty, i.e. put off the instruction execution for the branch, fill in other instructions (if possible)

RISC s use delayed loads to avoid waiting, i.e. insert an instruction that is independent of the load right after the load instruction and always executes it! (very similar idea to the use of delayed branches Pre-fetch branch-target to reduce the branch delay Use special cache to decrease memory-to-CPU delay Use optimizing compilers that can fill load-delay and branch-delay slots allocate registers to reduce result-register dependencies move load instruction as early as possible move instructions that evaluate branch addresses and branch condition test as early as possible to reduce branch penalty

The usual equation for determining performance is the sum for all instructions of (the number of cycles per instruction * instruction cycle time) = execution time.

This allows you to speed up a processor in 3 different ways --- use fewer instructions for a given task, reduce the number of cycles for some instructions, or speed up the clock (decrease the cycle time.) CISC tries to reduce the number of instructions for a program, and (as we will see) RISC tries to reduce the cycles per instruction.