[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Sep 15 Overall Project Objective : Dynamic Control The Traffic Lights

Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation (in processing)  Size estimates/  floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

Flow Chart Hold until n 1 or n 2 changes Light favours n 1 or n 2 ? n1n1 n2n2 T<r 1 ? T<r 2 ? T>= R 1 ?T>= R 2 ? n 1 =0? n 2 =0? f 1 <=0? f 2 <=0? Switch Light Set T = 0 No Yes No Yes No n 1, n 2 :# of cars T :Time spent in this phase r i : Min. time for each phase R i : Max. time for each phase f i : the control function f 1 = α 1 *n 1 + β 1 – n 2 f 2 = α 2 *n 2 + β 2 – n 1

Adder Subtractor Total Adder N1 Adder Clock Comparator r R zeroSwitch Light N2 F T Reset T zero T >= r ? T >= R ? N = 0 ? F <= 0 ? Accumulator Alpha & Beta Accumulator Arm 1 Arm 2 Compute N2 Control Signal to choose which arm operates Ni = number of cars queued F1(t) = α1N1(t) + β1 – N2(t) F2(t) = α2N2(t) + β2 – N1(t) T = time elapsed since last change of phase r, R = minimum, maximum allowable durations of phase for arm_i FUNCTION BLOCK SRAM [?]

n1s1 n1s2 n2s1 α1N1+β1 α2N2+β2 n1q1 n1q2 n2q1 N2 N1 FP SUB n11 n12 n21 f1 f2 n11 n21 α1N1 N_i FP ADD N1 N2 α2N2 n12 n22 β1 N_i β2 α1N1+β1 α2N2+β2 N_t_i α1 α2 N1 N2 FP MULT α1N1 α2N2 N_t1 N_t2 # of Phases 5 FP DIVIDE N_avg1 N_avg2 N_avg1 N_avg2 (from SRAM) β1 β2 ALU OPERATION

SRAM NiNi REWE x2 i = 1,2 counter # of phases Phase End reset 32 Reg en clk αiαi α start α in x2 32 Reg en clk βiβi β start β in x2 32 Reg clk N n i s j nisjnisj x8 32 Reg clk R i, r j x4

Transistor Count Estimates DevicesNumber of Transistors Divider + Sub15,000 Adder15,000 Multiplexer10,000 SRAM (?)6,500 MUX804 FSM2,000 Total49,304 Density : micro^2

Issues  Clock ?  SRAM or registers for storing old n values ?  IEEE 32 bit floating point format or a made up 16 bit floating point format?