CS 61C L17 Control (1) A Carle, Summer 2006 © UCB inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #17: CPU Design II – Control Andy Carle

CS 61C L17 Control (2) A Carle, Summer 2006 © UCB Anatomy: 5 components of any Computer Personal Computer Processor Computer Control (“brain”) Datapath (“brawn”) Memory (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running) This week

CS 61C L17 Control (3) A Carle, Summer 2006 © UCB Review: A Single Cycle Datapath Rs, Rt, Rd, Imed16 connected to datapath We have everything except control signals

CS 61C L17 Control (4) A Carle, Summer 2006 © UCB An Abstract View of the Critical Path Critical Path (Load Operation) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address This affects how fast you can clock your PC

CS 61C L17 Control (5) A Carle, Summer 2006 © UCB Recap: Meaning of the Control Signals nPC_MUX_sel: 0  PC <– PC  PC <– PC {SignExt(Im16), 00 } Later in lecture: higher-level connection between mux and branch cond Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel PC Ext imm16 “n”=next

CS 61C L17 Control (6) A Carle, Summer 2006 © UCB Recap: Meaning of the Control Signals ExtOp:“zero”, “sign” ALUsrc:0  regB; 1  immed ALUctr:“add”, “sub”, “or” °MemWr:1  write memory °MemtoReg: 0  ALU; 1  Mem °RegDst:0  “rt”; 1  “rd” °RegWr:1  write register 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal =

CS 61C L17 Control (7) A Carle, Summer 2006 © UCB RTL: The Add Instruction add rd, rs, rt MEM[PC]Fetch the instruction from memory R[rd] = R[rs] + R[rt]The actual operation PC = PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct bits 5 bits

CS 61C L17 Control (8) A Carle, Summer 2006 © UCB Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions PC Ext Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction

CS 61C L17 Control (9) A Carle, Summer 2006 © UCB The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 1 Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction R[rd] = R[rs] + R[rt] Imm16RdRsRt oprsrtrdshamtfunct nPC_sel= +4

CS 61C L17 Control (10) A Carle, Summer 2006 © UCB Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction 0 1

CS 61C L17 Control (11) A Carle, Summer 2006 © UCB Single Cycle Datapath during Or Immediate? oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel = R[rt] = R[rs] OR ZeroExt[Imm16]

CS 61C L17 Control (12) A Carle, Summer 2006 © UCB 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction R[rt] = R[rs] OR ZeroExt[Imm16] Imm16RdRsRt oprsrtimmediate nPC_sel= +4 Single Cycle Datapath during Or Immediate?

CS 61C L17 Control (13) A Carle, Summer 2006 © UCB The Single Cycle Datapath during Load? 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt R[rt] = Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate nPC_sel=

CS 61C L17 Control (14) A Carle, Summer 2006 © UCB The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt R[rt] = Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate nPC_sel= +4

CS 61C L17 Control (15) A Carle, Summer 2006 © UCB The Single Cycle Datapath during Store? oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel = Data Memory {R[rs] + SignExt[imm16]} = R[rt]

CS 61C L17 Control (16) A Carle, Summer 2006 © UCB The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt Data Memory {R[rs] + SignExt[imm16]} = R[rt] oprsrtimmediate nPC_sel= +4

CS 61C L17 Control (17) A Carle, Summer 2006 © UCB The Single Cycle Datapath during Branch? 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 oprsrtimmediate nPC_sel=

CS 61C L17 Control (18) A Carle, Summer 2006 © UCB The Single Cycle Datapath during Branch 32 ALUctr =Sub Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 oprsrtimmediate nPC_sel= “Br”

CS 61C L17 Control (19) A Carle, Summer 2006 © UCB Instruction Fetch Unit at the End of Branch if (Zero == 1) then PC = PC SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate What is encoding of nPC_sel? Direct MUX select? Branch / not branch Let’s pick 2nd option Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel Q: What logic gate?

CS 61C L17 Control (20) A Carle, Summer 2006 © UCB Step 4: Given Datapath: RTL -> Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Zero Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

CS 61C L17 Control (21) A Carle, Summer 2006 © UCB A Summary of the Control Signals (1/2) inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel =“+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

CS 61C L17 Control (22) A Carle, Summer 2006 © UCB A Summary of the Control Signals (2/2) addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr x Add x Subtract Or Add x 1 x x 0 x x Subtract x x x x xxx optarget address oprsrtrdshamtfunct oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op Appendix A See We Don’t Care :-)

CS 61C L17 Control (23) A Carle, Summer 2006 © UCB Administrivia Project 2 Due Friday HW 5 Now Available

CS 61C L17 Control (24) A Carle, Summer 2006 © UCB 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt New PC = { PC[31..28], target address, 00 } nPC_sel= The Single Cycle Datapath during Jump optarget address J-typejump 25 Jump= TA26

CS 61C L17 Control (25) A Carle, Summer 2006 © UCB The Single Cycle Datapath during Jump 32 ALUctr =x Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = x ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction RdRsRt New PC = { PC[31..28], target address, 00 } nPC_sel=0 Jump=1 Imm16 TA26 optarget address J-typejump 25

CS 61C L17 Control (26) A Carle, Summer 2006 © UCB Instruction Fetch Unit at the End of Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel New PC = { PC[31..28], target address, 00 } optarget address J-typejump 25 How do we modify this to account for jumps? Jump

CS 61C L17 Control (27) A Carle, Summer 2006 © UCB Instruction Fetch Unit at the End of Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel New PC = { PC[31..28], target address, 00 } optarget address J-typejump 25 Mux 1 0 Jump TA26 4 (MSBs) 00 Query Can Zero still get asserted? Does nPC_sel need to be 0? If not, what?

CS 61C L17 Control (28) A Carle, Summer 2006 © UCB Build CL to implement Jump on paper now Jump Inst31 Inst30 Inst29 Inst28 Inst27 Inst26 Inst25 Inst01 Inst00

CS 61C L17 Control (29) A Carle, Summer 2006 © UCB Build CL to implement Jump on paper now Jump Inst31 Inst30 Inst29 Inst28 Inst27 Inst26 Inst25 Inst01 Inst00 2-input 6-bit-wide XNOR A B 6-input AND AiAi BiBi XNOR

CS 61C L17 Control (30) A Carle, Summer 2006 © UCB Peer Instruction A. MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ? B. ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp? C. “Don’t Care” signals are useful because we can simplify our Boolean equations?

CS 61C L17 Control (31) A Carle, Summer 2006 © UCB °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °MIPS makes that easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates And in Conclusion… Single cycle control Control Datapath Memory Processor Input Output