DSP Lab at FEUP-DEEC 1 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 Grasping the Potencial of Digital Signal Laboratory Processing through Real-Time DSP Laboratory Experiments Aníbal J. S. Ferreira*^, Francisco J. O. Restivo* * Faculdade de Engenharia da Universidade do Porto Departamento de Engenharia Electrotécnica e Computadores Rua Dr. Roberto Frias, Porto, Portugal ^ INESC Porto, Portugal

DSP Lab at FEUP-DEEC 2 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 Abstract A new DSP laboratory course has been included in the Electrical and Computer Engineering curriculum at the Faculdade de Engenharia da Universidade do Porto, in Portugal, since the school year of 1999/2000. This paper addresses the context and motivation underlying this new course, outlines its structure and methodology, highlights the design and goals of all DSP experiments currently proposed for the 13 weeks of the semester, and reports on the receptivity students have expressed to this elective course. The course is based on the TI C31 Starter Kit and tries to combine full use of its resources with a representative diversity of efficient digital signal processing techniques and associated application scenarios. A perspective is also given on current plans to reinforce DSP expertise at the graduate level.

DSP Lab at FEUP-DEEC 3 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 Summary EEC at FEUP-DEEC –basic structure and topics basic to DSP –EEC4162 (PDS) EEC5274 (PDSTR) –focus, rational, history –C31 starter kit –course structure and organization –DSP laboratory experiments –students feed-back Looking Forward –new challenges Conclusion

DSP Lab at FEUP-DEEC 4 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC at FEUP-DEEC basic structure –1st and 2nd year core –3rd year students select a branch APEL: industrial automation, production and electronic systems E: energy systems TEC: telecommunication, electronic and computer systems –4th and 5th year: mandatory + elective disciplines per branch basic structure –1st and 2nd year core –3rd year students select a branch APEL: industrial automation, production and electronic systems E: energy systems TEC: telecommunication, electronic and computer systems –4th and 5th year: mandatory + elective disciplines per branch 1st Year 2nd Year 3rd Year TEC 3rd Year APEL 3rd Year E PDS PDSTR 5th Year TEC 5th Year APEL 5th Year E 4th Year TEC 4th Year APEL 4th Year E

DSP Lab at FEUP-DEEC 5 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC at FEUP-DEEC basics to DSP during the first 3 years: –programming –Fourier transform / Fourier analysis –Laplace transform –Z transform –sampling / modulation –filtering –random processes –noise other topics: basics to DSP during the first 3 years: –programming –Fourier transform / Fourier analysis –Laplace transform –Z transform –sampling / modulation –filtering –random processes –noise other topics: digital systems signal theory circuit theory systems theory algorithms and data structures microprocessors probability and statistics telecommunications

DSP Lab at FEUP-DEEC 6 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC4162 (PDS) syllabus –3-hour class / week : theory + illustrative problems –2-hour class / week : problems, application of theory, –6 individual work assignments / semester ( e.g., using Matlab ) –main topics: discrete signals and systems sampling and reconstruction of analogue signals linear-time invariant systems structures for the realization of LTI systems FIR and IIR filter design finite word length effects decimation and interpolation the discrete Fourier transform overlap-add and overlap-save methods of FFFD response of LTI systems to random discrete signals FFT and its implementation syllabus –3-hour class / week : theory + illustrative problems –2-hour class / week : problems, application of theory, –6 individual work assignments / semester ( e.g., using Matlab ) –main topics: discrete signals and systems sampling and reconstruction of analogue signals linear-time invariant systems structures for the realization of LTI systems FIR and IIR filter design finite word length effects decimation and interpolation the discrete Fourier transform overlap-add and overlap-save methods of FFFD response of LTI systems to random discrete signals FFT and its implementation

DSP Lab at FEUP-DEEC 7 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC4162 (PDS) teaching experience reveals that –typically, a pencil and paper approach, even if complemented with simulation exercises using Matlab, is not enough for the student to grasp the advantage and potential of digital signal processing in many application areas including multimedia, telecommunications, control, and consumer electronics –as a consequence, a hands-on DSP laboratory course has been included, since 1999, in the EEC curriculum, so as to motivate students to explore DSP based solutions to practical problems such as filtering, Fourier analysis or Single Side Band Modulation (SSB) teaching experience reveals that –typically, a pencil and paper approach, even if complemented with simulation exercises using Matlab, is not enough for the student to grasp the advantage and potential of digital signal processing in many application areas including multimedia, telecommunications, control, and consumer electronics –as a consequence, a hands-on DSP laboratory course has been included, since 1999, in the EEC curriculum, so as to motivate students to explore DSP based solutions to practical problems such as filtering, Fourier analysis or Single Side Band Modulation (SSB)

DSP Lab at FEUP-DEEC 8 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) profile –elective course based on DSP laboratory experiments –offered during the 8th semester of the EEC curriculum –part of the EEC curriculum since 1999 –student preference 1999/2000: 16 students 2000/2001: 32 students 2001/2002: 22 students –focus practical digital signal processing issues and applications efficient realization structures real-time processing constraints –approach advantages of DSP are demonstrated by lab examples covering a representative diversity of application scenarios student is challenged with specific DSP design and realization issues. profile –elective course based on DSP laboratory experiments –offered during the 8th semester of the EEC curriculum –part of the EEC curriculum since 1999 –student preference 1999/2000: 16 students 2000/2001: 32 students 2001/2002: 22 students –focus practical digital signal processing issues and applications efficient realization structures real-time processing constraints –approach advantages of DSP are demonstrated by lab examples covering a representative diversity of application scenarios student is challenged with specific DSP design and realization issues.

DSP Lab at FEUP-DEEC 9 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) selected DSP laboratory platform: C31 starter Kit –DSP initialization kit able to realize many different laboratory experiments running in real-time –includes assembler and ( windows-based ) debugger environment (Go-DSP Code Explorer) –availability of many demonstration code examples and support (C31 teaching kit), and literature –kind support of the Texas Instruments European University Programme selected DSP laboratory platform: C31 starter Kit –DSP initialization kit able to realize many different laboratory experiments running in real-time –includes assembler and ( windows-based ) debugger environment (Go-DSP Code Explorer) –availability of many demonstration code examples and support (C31 teaching kit), and literature –kind support of the Texas Instruments European University Programme

DSP Lab at FEUP-DEEC 10 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) modus operandi –1.5 hour class / week theory, demonstration of concepts –2.5 hour class / week laboratory work: design, realization and performance assessment of algorithms running in real-time –students are encouraged to keep the kit between classes eases preparation for the lab work opportunity for students to explore beyond the strict realization goals of each lab work self-learning modus operandi –1.5 hour class / week theory, demonstration of concepts –2.5 hour class / week laboratory work: design, realization and performance assessment of algorithms running in real-time –students are encouraged to keep the kit between classes eases preparation for the lab work opportunity for students to explore beyond the strict realization goals of each lab work self-learning

DSP Lab at FEUP-DEEC 11 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) theory and laboratory classes –first part (theory) use of the development environment of the C31: assembler, debugger, C31 architecture, peripherals and instruction set –second part (theory) real-time realization of algorithms for FIR; IIR and FIR-adaptive filtering, multirate processing using polyphase decomposition, FFT and spectral analysis, SSB modulation (Hilbert Transform) –laboratory classes 10 lab experiments and reports during the 13-week semester each report: main results and conclusions of each lab work early feed-back is given to students theory and laboratory classes –first part (theory) use of the development environment of the C31: assembler, debugger, C31 architecture, peripherals and instruction set –second part (theory) real-time realization of algorithms for FIR; IIR and FIR-adaptive filtering, multirate processing using polyphase decomposition, FFT and spectral analysis, SSB modulation (Hilbert Transform) –laboratory classes 10 lab experiments and reports during the 13-week semester each report: main results and conclusions of each lab work early feed-back is given to students Week n goals for week n+1 revealed on web site students hand-over short report at end of each lab class report (corrected and graded) of previous week is returned to students

DSP Lab at FEUP-DEEC 12 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) syllabus –presumes the core knowledge of the pre-requisite DSP course (EEC 4162), including efficient realization structures and FFT –new topics: filter banks, uniform filter banks and their relation to the DFT half-band filters, M-band filters, power complementary filters the QMF filter bank, design and implementation issues, multi- resolution analysis using the QMF adaptive filtering polyphase decomposition of interpolation and decimation filters and their efficient realization Hilbert Transformer and SSD modulation syllabus –presumes the core knowledge of the pre-requisite DSP course (EEC 4162), including efficient realization structures and FFT –new topics: filter banks, uniform filter banks and their relation to the DFT half-band filters, M-band filters, power complementary filters the QMF filter bank, design and implementation issues, multi- resolution analysis using the QMF adaptive filtering polyphase decomposition of interpolation and decimation filters and their efficient realization Hilbert Transformer and SSD modulation

DSP Lab at FEUP-DEEC 13 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) laboratory experiments caracterization of the problem DSP conceptual approach validation in Matlab identification of opportunities for efficient realization assembly code debugging performance assessment

DSP Lab at FEUP-DEEC 14 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 1. verification of the aliasing in sampling –goal: estimate the sampling frequency just by hearing the result at the output of the system, due to a sinusoid of varying (and known) frequency that is injected at the input 1. verification of the aliasing in sampling –goal: estimate the sampling frequency just by hearing the result at the output of the system, due to a sinusoid of varying (and known) frequency that is injected at the input A/D D/A C31 AAFAIF ON/OFF

DSP Lab at FEUP-DEEC 15 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 2. waveform generation and converter testing –goal: take advantage of circular addressing in order to synthesize different waveformss, and of the lookp-back mode of AIC in order to evaluate the accumulated quality of the D/A and A/D conversion (delay, noise floor, differential non-linearity) 2. waveform generation and converter testing –goal: take advantage of circular addressing in order to synthesize different waveformss, and of the lookp-back mode of AIC in order to evaluate the accumulated quality of the D/A and A/D conversion (delay, noise floor, differential non-linearity) A/D D/A C31 AAFAIF

DSP Lab at FEUP-DEEC 16 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 3. fixed point processing vs. floating point processing –goal: identify issues of fixed representation of numbers (namely the need for scaling) in recursive processing, versus floating-point 3. fixed point processing vs. floating point processing –goal: identify issues of fixed representation of numbers (namely the need for scaling) in recursive processing, versus floating-point sin(n) cos(n) sin[(n+1)] cos[(n+1)] c1 c2 c3 c4

DSP Lab at FEUP-DEEC 17 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 4. FIR filtering –goal 1: H(z)=1-z -15, compare theoretical H(e j  ) vs. experimental –goal 2: realization of FIR equiripple h(n), 2h(n)cos n  /2, (-1) n h(n) 4. FIR filtering –goal 1: H(z)=1-z -15, compare theoretical H(e j  ) vs. experimental –goal 2: realization of FIR equiripple h(n), 2h(n)cos n  /2, (-1) n h(n)   /2     

DSP Lab at FEUP-DEEC 18 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 5. IIR filtering –goal 1: 6th order IIR, type 2 realization structure –goal 2: compare simulated response vs. experimental response 5. IIR filtering –goal 1: 6th order IIR, type 2 realization structure –goal 2: compare simulated response vs. experimental response Z Z b0b0 b1b1 a1a1 Z b M-1 a N-1 x(n)y(n)

DSP Lab at FEUP-DEEC 19 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 6. five vowel synthesizer –goal: synthesize /à/, /é/, /i/, /ó/, /u/ on a DSK using three formants didactic application allows to give each implementation a personal flavor ( high motivation impact ) quality improvements by modulating pitch 6. five vowel synthesizer –goal: synthesize /à/, /é/, /i/, /ó/, /u/ on a DSK using three formants didactic application allows to give each implementation a personal flavor ( high motivation impact ) quality improvements by modulating pitch

DSP Lab at FEUP-DEEC 20 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 7. interpolation using polyphase filters –goal: efficient realization of interpolation filter, experimental evaluation of of the sinc function associated to the D/A reconstruction when 4-fold interpolation is used and when not 7. interpolation using polyphase filters –goal: efficient realization of interpolation filter, experimental evaluation of of the sinc function associated to the D/A reconstruction when 4-fold interpolation is used and when not   /4 44 A/D D/A C31 AAFAIF x(n) R 2 (z) R 1 (z) R 3 (z) n=0 n=1 n=2 R 0 (z) n=3 

DSP Lab at FEUP-DEEC 21 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 8. adaptive filtering –goal 1: realization and assessment of the operation of an adaptive filter (32 tap FIR, LMS) –goal 2: implementation of the configuration insuring real-time echo canceling 8. adaptive filtering –goal 1: realization and assessment of the operation of an adaptive filter (32 tap FIR, LMS) –goal 2: implementation of the configuration insuring real-time echo canceling gZ -1 adaptive filter A/D D/A gZ -1 adaptive filter - A/D D/A what are the differences ?

DSP Lab at FEUP-DEEC 22 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 9. FFT assembly implementation –goal 1: assembly implemention of a radix-2 FFT based on a C- like optimized (Matlab) code (N=64) –goal 2: assessment of the implementation when used as a simple real-time spectrum analyser 9. FFT assembly implementation –goal 1: assembly implemention of a radix-2 FFT based on a C- like optimized (Matlab) code (N=64) –goal 2: assessment of the implementation when used as a simple real-time spectrum analyser

DSP Lab at FEUP-DEEC 23 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) - Lab experiments 10. single side band modulation –goal: design and realization of a band-pass filter, Hilbert transformer, SSB modulator based on analytic signal generation 10. single side band modulation –goal: design and realization of a band-pass filter, Hilbert transformer, SSB modulator based on analytic signal generation         down-shift up-shift spectral-inversion

DSP Lab at FEUP-DEEC 24 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 EEC5274 (PDSTR) students feed-back –plus: tangible and intuitive linking between theory and practice methodology elicits insight and promotes application –minus more time to prepare and to “play” sooner indication of lab work description lab classes > 2,5 hours –regarding possibility of additional DSP lab course 50% say yes if addressing more application scenarios and combining video and audio students feed-back –plus: tangible and intuitive linking between theory and practice methodology elicits insight and promotes application –minus more time to prepare and to “play” sooner indication of lab work description lab classes > 2,5 hours –regarding possibility of additional DSP lab course 50% say yes if addressing more application scenarios and combining video and audio

DSP Lab at FEUP-DEEC 25 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 Looking Forward new challenges –new starter kit ? VLIW TMS320C6711 ? –new DSP issues utilization of cache utilization of DMA combined C, assembly code optimization new challenges –new starter kit ? VLIW TMS320C6711 ? –new DSP issues utilization of cache utilization of DMA combined C, assembly code optimization

DSP Lab at FEUP-DEEC 26 AJF/FJR 2nd IEEE SPE, October 13-16, GA, 2002 Conclusion PDSTR: an ECE advanced undergraduate level DSP laboratory course –all course material (in Portuguese) is available on the Web –hands-on DSP laboratory experience consolidates knowledge stimulates criativity helps to develop a rewarding sense of achievement motivates final-year course projects using DSP technology –plans for a new DSP lab (C6711) at the graduate level focus on complex and complete algorithm implementation PDSTR: an ECE advanced undergraduate level DSP laboratory course –all course material (in Portuguese) is available on the Web –hands-on DSP laboratory experience consolidates knowledge stimulates criativity helps to develop a rewarding sense of achievement motivates final-year course projects using DSP technology –plans for a new DSP lab (C6711) at the graduate level focus on complex and complete algorithm implementation