Design and Implementation of VLSI Systems (EN1600) lecture02 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

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Presentation transcript:

Design and Implementation of VLSI Systems (EN1600) lecture02 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey Pearson]

Impact of doping on silicon resistivity dope with phosphorous or arsenic  n-type dope with boron  p-type silicon  atoms in cm 3 Resistivity 3.2  10 5 Ωcm 1 atom in billion  88.6 Ωcm 1 atom in million  Ωcm 1 atom in thousand  Ωcm 1 atom in billion  Ωcm 1 atom in million  Ωcm 1 atom in thousand  Ωcm  Electrons are more mobile/faster than holes

What happens if we sandwich p & n types? n p A B Al One-dimensional representation  In equilibrium, the drift and diffusion components of current are balanced; therefore the net current flowing across the junction is zero.

PN-junction regions of operation In reverse bias, the width of the depletion region increases. The diode acts as voltage-controlled capacitor. A forward bias decreases the potential drop across the junction. As a result, the magnitude of the electric field decreases and the width of the depletion region narrows.

nMOS and pMOS transistors nMOS transistorpMOS transistor Each transistor consists of a stack of a conducting gate, an insulating layer of silicon dioxide and a semiconductor substrate (body or bulk) Body is typically groundedBody is typically at supply voltage

nMOS transistor g=0: When the gate is at a low voltage (V GS < V TN ):  p-type body is at low voltage  source and drain-junctions diodes are OFF  transistor is OFF, no current flows g=1: When the gate is at a high voltage (V GS ≥ V TN ):  negative charge attracted to body  inverts a channel under gate to n-type  transistor ON, current flows, transistor can be viewed as a resistor

nMOS pass ‘0’ more strongly than ‘1’ Why does ‘1’ pass degraded?

pMOS transistor g=0: When the gate is at a low voltage (V GS < V TP ):  positive charge attracted to body  inverts a channel under gate to p-type  transistor ON, current flows g=1: When the gate is at a high voltage (V GS ≥ V TP ):  negative charge attracted to body  source and drain junctions are OFF  transistor OFF, no current flows

pMOS pass ‘1’ more strongly than ‘0’ Why does ‘0’ pass degraded?

An nMOS and pMOS make up an inverter pMOS + nMOS = CMOS

More CMOS gates What is this gate function? What’s wrong about this design?

3-input NANDs What are the advantages of CMOS circuit style?

Series-Parallel Combinations

What are the transistor schematics of the NOR gate?

AOI

Transmission gate