The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov The Belle SVD Trigger Tom Ziegler on behalf of the Belle SVD group  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov 2002  The SVD 2.0 Update  The Front-End Readout Electronics  Level 0 & 1 Trigger  Level 1.5 Trigger  Summary

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov The Belle detector SVD 1.4 SVD 2.0

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov Update SVD 1.4 => SVD 2.0  Increase radiation hardness of the front-end readout chip: 0.8  m => 0.35  m CMOS process  Stable > 10 MRad!  Better polar angle coverage: 23°-139° => 17°-150°  Closer to beam pipe (  3->2.1cm)  increasing peak luminosity:  cm -2 s -1 (28-oct-2002)  Include trigger capability in front-end chip

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov The Readout Electronics Repeater System FADC PCI and DAQ Trigger L0&L1 Trigger L1.5 DSSD Hybrid, VA1TA 4 layers (6, 12, 18, 18)  54 ladders,  108 halfladders (108*512)*2 = channels

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov Each chip reads out 128 DSSD channels. Trigger capability is included in the ASIC. FE readout chips: VA1TA, IDE AS Front-end Electronics slow Shaper S/H Multiplexer PA HoldAnalog out 128x fast Shaper Threshold Discr. 128x Trigger out 1x !

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov The Readout Electronics Repeater System FADC PCI and DAQ Trigger L0&L1 Trigger L1.5 DSSD Hybrid, VA1TA 4 layers (6, 12, 18, 18)  54 ladders,  108 half ladders (108*512)*2 = channels TA signal, granularity of 128 strips

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov ToF trigger CDC trigger SVD TA CDC SVD-CDC matching Global L1 Global L0 Level 0 and Level 1 Trigger We take advantage of the trigger capabilities of the front-end readout electronics (VA1TA). Resolution not very good, but very fast decision possible ( <600ns for L0 / <2.5  s for L1). Other SubS.

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov The Readout Electronics Repeater System FADC PCI and DAQ Trigger L0&L1 Trigger L1.5 DSSD Hybrid, VA1TA 4 layers (6, 12, 18, 18)  54 ladders,  108 half ladders (108*512)*2 = channels VA analog signals, full granularity

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov The Level 1.5 r-z-Trigger After 25  s all information are available from the FADC- system and can be used for a trigger 1.5 decision with a very good tracking resolution! Mainly reject beam gas events that do not come from the primary vertex. Generate MC events and record ‘trigger terms’ for each of 18 wedges.  3.2cm wedge IP

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov The Trigger Logic Resolution which probably will be used: Layer 1/4: merge 32 strips to 16 segments on each wafer Layer 2/3: merge 16 strips to 32 segments on each wafer We see all the gaps between wafers. Single track efficiency < 80%! => 4/4 too simplistic Goal: at least 90% 

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov Improve efficiency Consider 3/4 terms (one layer missing) => 98% efficient, but not very good rejection of background events! Try 3/4 terms and demand 1. layer => Overall efficiency  95% in good region (but more than 20,000 trigger terms).  

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov Some statistical tricks Some of the logic terms are contained in others, e.g.: Reduce number of terms by  25%. Number of hits in each trigger term in simulation, e.g.: x x x x Skip all trigger terms with few hits! => skip terms without losing much efficiency

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov /4 terms 79.8%21449 terms 3/4 terms98.0%23867 terms 3/4 terms (with inner layer)95.3%23867 terms strip terms contained in others95.3%13474 terms strip terms with #hits <5095.3%10105 terms strip terms with #hits < %8272 terms strip terms with #hits < %5452 terms strip terms with #hits < %2497 terms Implementation of trigger logic in Xilinx FPGAs on a 9U VME board. single track efficiency number of trigger terms Implementation of Trigger Logic

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov Further improvement FADCDOCK TDM T1.5 data Level 1.5 trigger decision CDC ToF Up to 128 bits Up to 64 bits T1.5BB 1 bit for each of the 18 sectors Start of data transfer TTM SEQ GDL monitoring FEC data Introduce Trigger 1.5 Buffer Board Merging of SVD with CDC and ToF information!

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov The Trigger System The different trigger levels will be: L0  0.6  sSVD, ToF, CDC< 10kHz L1  2.5  sSVD, CDC, ECL< 1kHz L1.5  25  sSVD, (ToF, CDC) DAQ read-out The SVD will play a central role in the Belle trigger system!

The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8 th nov Summary l Upgrade to SVD 2.0 allows substantial improvements in the trigger capabilities for the Belle detector! l The implementation of the system with Xilinx FPGAs and overall setup is very flexible and there is still room for improvement to deal with the increasing luminosities of the KEKB accelerator. l The system will be tested the next months in an overall system integration test with the rest of the SVD readout system and is ready for installation in the next shutdown.