ELEN 468 Lecture 71 ELEN 468 Advanced Logic Design Lecture 7 System Tasks, Functions, Syntax and Behavioral Modeling I

ELEN 468 Lecture 72 System Tasks and Functions

ELEN 468 Lecture 73 Display Tasks $monitor $monitor(“%d %f %b %b”, $time, $realtime, x, y); Continuously display values $display, $displayb, $displayo, $displayh $display(“x = %b y = %b”, x, y); Display once only $write, $writeb, $writeo, $writeh $write(“x = %b y = %b”, x, y); Same as display, but no “\n”

ELEN 468 Lecture 74 Files $fopen, $fclose, $fdisplay module test_bench(); reg x; wire y; integer cd; assign y = ~x; initial begin cd = $fopen("test.dat"); #100 x = 0; $fdisplay(cd, "%b %b", x, y); $fclose(cd); end endmodule module test_bench(); reg x; wire y; integer cd; assign y = ~x; initial begin cd = $fopen("test.dat"); #100 x = 0; $fdisplay(cd, "%b %b", x, y); $fclose(cd); end endmodule channel descriptor

ELEN 468 Lecture 75 Read Memory parameter ram_file = “ram_data_file”; reg [15:0] RAM_1 [0:1023]; initial $readmemh(ram_file, RAM_1); // read input file as hexadecimal initial $readmemb(ram_file, RAM_1); // read input file as binary parameter ram_file = “ram_data_file”; reg [15:0] RAM_1 [0:1023]; initial $readmemh(ram_file, RAM_1); // read input file as hexadecimal initial $readmemb(ram_file, RAM_1); // read input file as binary

ELEN 468 Lecture 76 Simulation Control $finish and $finish(n) n = 0, print nothing n = 1, print simulation time and location n = 2, print simulation time, location and statistics $stop(n): interactive mode initial #200 $finish; initial #200 $finish; initial begin #20 x=0; y=0; $stop(0); initial begin #20 x=0; y=0; $stop(0);

ELEN 468 Lecture 77 Probability Distribution Generate different types of distributions integer seed, d; d = $dist_uniform(seed, 0, 9); d = $dist_exponential(seed, 3); d = $dist_normal(seed, 0, 5); integer seed, d; d = $dist_uniform(seed, 0, 9); d = $dist_exponential(seed, 3); d = $dist_normal(seed, 0, 5); range mean standard deviation

ELEN 468 Lecture 78 Compiler Directives `timescale `include `defaultnettype `define and `undef `ifdef, `else, `endif `include “testbench.v” `defaultnettype wor `define wait_state 3’b010 `undef wait_state `ifdef BEHAVIORAL y = x1 | x2; `else or ( y, x1, x2 ); `endif `include “testbench.v” `defaultnettype wor `define wait_state 3’b010 `undef wait_state `ifdef BEHAVIORAL y = x1 | x2; `else or ( y, x1, x2 ); `endif

ELEN 468 Lecture 79 Syntax

ELEN 468 Lecture 710 BNF Formal Syntax Notation BNF = Backus-Naur Form or Backus Normal Form ::= definition of syntax | alternative syntax […] appear once or not at all {…} appear any times, or not at all

ELEN 468 Lecture 711 Example of Verilog Syntax source_text ::= { description } description ::= module_declaration | udp_declaration module_declaration ::= module_keyword module_identifier [list_of_ports]; { module_item } endmodule module_keyword ::= module | macromodule

ELEN 468 Lecture 712 list_of_ports ::= ( port {, port} ) module_item ::= module_item_declaration | parameter_overwrite | continuous_assign | gate_instantiation | udp_instantiation | module_instantiation | specify_block | initial_construct | always_construct

ELEN 468 Lecture 713 continuous_assign ::= assign [drive_strength] [delay3] list_of_net_assignments; drive_strength ::= ( strength0, strength1) delay3 ::= #delay_value | #(delay_value [, delay_value [, delay_value]] ) list_of_net_assignments ::= net_assignment {, net_assignment } net_assignment ::= net1_value = expression

ELEN 468 Lecture 714 Behavioral Modeling I

ELEN 468 Lecture 715 Structural vs. Behavioral Descriptions module my_module(…); … assign …; // continuous assignment and (…); // instantiation of primitive adder_16 M(…); // instantiation of module begin … end initial begin … end endmodule Structural, no order Behavior, in order in each procedure

ELEN 468 Lecture 716 Behavioral Procedural Behavioral Descriptions In General Co-exists with gate instantiations Not all descriptions synthesize Not all synthesized descriptions are desirable Non-structural behaviors Continuous assignment initial always Within a module Multiple behaviors are allowed Nested behaviors are not allowed

ELEN 468 Lecture 717 Behavioral Statements initial | always single_statement; | begin block_of_statements; end initial | always single_statement; | begin block_of_statements; end initial Activated from t sim = 0 Executed once Initialize a simulation always Activated from t sim = 0 Executed cyclically Continue till simulation terminates

ELEN 468 Lecture 718 Example of Behavioral Statement module clock1 ( clk ); parameter half_cycle = 50; parameter max_time = 1000; output clk; reg clk; initial clk = 0; always begin #half_cycle clk = ~clk; end initial #max_time $finish; endmodule module clock1 ( clk ); parameter half_cycle = 50; parameter max_time = 1000; output clk; reg clk; initial clk = 0; always begin #half_cycle clk = ~clk; end initial #max_time $finish; endmodule clk t sim

ELEN 468 Lecture 719 Assignment Continuous assignment Values are assigned to net variables due to some input variable changes “assign …=… “ Procedural assignment Values are assigned to register variables when certain statement is executed in a behavior Procedural assignment, “=“ Procedural continuous assignment, “assign …=… [deassign] “ Non-blocking assignment, “<=“

ELEN 468 Lecture 720 Blocking and Non-blocking Assignment initial begin a = 1; b = 0; a = b; // a = 0; b = a; // b = 0; end initial begin a = 1; b = 0; a <= b; // a = 0; b <= a; // b = 1; end Blocking assignment “=“ Statement order matters A statement has to be executed before next statement Non-blocking assignment “<=“ Concurrent assignment If there are multiple non- blocking assignments to same variable in same behavior, latter overwrites previous

ELEN 468 Lecture 721 Procedural Continuous Assignment Continuous assignment establishes static binding for net variables Procedural continuous assignment (PCA) establishes dynamic binding for variables “assign … deassign” for register variables only “force … release” for both register and net variables

ELEN 468 Lecture 722 “assign … deassign” PCA Binding takes effect when PCA statement is executed Can be overridden by another PCA statement “deassign” is optional “assign” takes control, “deassign” release control module flop ( q, qbar, preset, clear, clock, data ); … assign qbar = ~q; initial q = 0; ( negedge clk ) q = data; ( clear or preset ) begin if ( !preset ) assign q = 1; else if ( !clear ) assign q = 0; else deassign q; end endmodule module flop ( q, qbar, preset, clear, clock, data ); … assign qbar = ~q; initial q = 0; ( negedge clk ) q = data; ( clear or preset ) begin if ( !preset ) assign q = 1; else if ( !clear ) assign q = 0; else deassign q; end endmodule

ELEN 468 Lecture 723 Example of assign module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out; begin if (select == 0) assign y_out=a; else if (select == 1) assign y_out=b; else if (select == 2) assign y_out=c; else if (select == 3) assign y_out=d; else assign y_out=1’bx; end endmodule module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out; begin if (select == 0) assign y_out=a; else if (select == 1) assign y_out=b; else if (select == 2) assign y_out=c; else if (select == 3) assign y_out=d; else assign y_out=1’bx; end endmodule y_out changes with a;

ELEN 468 Lecture 724 Alternative module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out; or a or b or c or d) begin if (select == 0) y_out=a; else if (select == 1) y_out=b; else if (select == 2) y_out=c; else if (select == 3) y_out=d; else y_out=1’bx; end endmodule module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out; or a or b or c or d) begin if (select == 0) y_out=a; else if (select == 1) y_out=b; else if (select == 2) y_out=c; else if (select == 3) y_out=d; else y_out=1’bx; end endmodule Value of ‘a’ is assigned to y_out at this time

ELEN 468 Lecture 725 “force … release” PCA force sig1 = 0; force sig2 = 1; Sig3 = 0; #9 sig3 = 1; … release sig1; release sig2; force sig1 = 0; force sig2 = 1; Sig3 = 0; #9 sig3 = 1; … release sig1; release sig2; Similar to “assign…deassign” Can be applied to net variables Often applied in testing modA modB sig1 sig2 sig3

ELEN 468 Lecture 726 Comparisons of Assignment mode Output of primitive Continuous assignment Procedural assignment assign … deassign PCA force … release PCA VariableNet Seq-reg NetRegister Net and register descriptionStructural Behavioral bindingStatic Dynamic, one shot Dynamic, continuous