1 Pertemuan 23 Reduced Instruction Set Computer 1 Matakuliah: H0344/Organisasi dan Arsitektur Komputer Tahun: 2005 Versi: 1/1.

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Presentation transcript:

1 Pertemuan 23 Reduced Instruction Set Computer 1 Matakuliah: H0344/Organisasi dan Arsitektur Komputer Tahun: 2005 Versi: 1/1

2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Menjelaskan prinsip kerja Reduced Instruction Set Computer

3 Outline Materi Instruction Execution Characteristics The Use of Large Register File Compiler-Based Register Optimization Reduced Instruction Set Architecture RISC Pipelining RISC versus CISC Controversy

4 Overview Key element of RISC: 1.A large number of general purpose registers, and/or the use of compiler technology to optimize register usage. 2.A limited and simple instruction set. 3.An emphasis on optimizing the instruction pipeline.

5 CISCRISCSuperscalar Characteristic IBM 370/168 VAX 11/780 Intel SPARC MIPS R4000 PowerPC Ultra SPARC MIPS R1000 Year developed Number of instructions Instruction size (byte) Addressing modes Number of general purpose registers Control memory size (kbits) Cache size (kbyte) Overview

6 Instruction Execution Characteristics The major cost in the life cycle of system is software, not hardware. Researchers and industry have been to develop ever more powerful and complex high level programming languages. These high level language (HLLs) allow the programmer to express algorithms more concisely, take care more detail, and often support naturally the use of structured programming or object oriented design.

7 Instruction Execution Characteristics Operations performed Study language workload [HUCH83][KNUT71][PATT82][TANE78] Pascal Scientific Fortran Student Pascal System C System Sal System Assign Loop43534 Call If Goto29-3- Other-7616 Relative dynamic frequency of high level language operations

8 Instruction Execution Characteristics Operations performed % Dynamic Occurrence Machine instruction weighted Memory reference weighted PascalC C C Assign Loop Call If Goto Other Weighted relative dynamic frequency of HLL operation

9 Instruction Execution Characteristics Operands used Dynamic percentage of operands %PascalCAverage Integer constant Scalar variable Array/structure262425

10 Instruction Execution Characteristics Procedure calls Procedure arguments and local scalar variables Percentage of executed procedure calls with Compiler, interpreter, and typesetter Small nonnumeric program >3 arguments >5 arguments0-30 >8 words of arguments and local scalars >12 word of arguments and local scalar

11 Instruction Execution Characteristics Implication 1.Use a large number of registers or use a compiler to optimize register usage. 2.Careful attention need to be paid to the design of instruction pipelines. 3.A simplified (reduced) instruction set is indicated.

12 The use of a large register file The most accesses are to local scalars. 1.The software approach is to rely on compiler to maximize register usage. 2.The hardware approach is simply to use more register so that more variables can be held in registers for longer periods of time. A strategy is needed that will allow the most frequently accessed operands to be kept in registers and to minimize register-memory operations.

13 The use of a large register file Register windows 1.A typical procedure employs only a few passed parameters and local variable 2.The depth of procedure activation fluctuates within a relative narrow range. The facts:

14 The use of a large register file Register windows Overlapping register windows

15 The use of a large register file Register windows Circular buffer organization of overlapped windows

16 The use of a large register file Large register file versus cache Characteristics of large register file and cache organizations Large register fileCache All local scalarsRecently used local scalars Individual variablesBlocks of memory Compiler assigned global variablesRecently used global variables Save/restore based on procedure nesting depth Save/restore based on cache replacement algorithm Register addressingMemory addressing

17 The use of a large register file Large register file versus cache Referencing a scalar

18 Compiler based register optimization Graph coloring approach