Implement UART core on FPGA The High Speed Digital Systems Laboratory Electrical Engineering Faculty, Technion By: Marganit Fina Supervisor: Rivkin Ina Winter 2006/7 Duration: Semester Characterization Presentation

Project purpose Implement an 8250 UART core on an FPGA – Write a UART Core in VHDL, that can be used in other projects – Write a core environment test

System view

UART - Universal Asynchronous Receiver- Transmitter Converts the bytes it receives from the computer along parallel circuits into a single serial bit stream for outbound transmissionparallelserial On inbound transmission, converts the serial bit stream into the bytes that the computer handles Adds a parity bit on outbound transmissions and checks the parity of incoming bytes and discards the parity bitparity Adds start and stop delineators on outbound and strips them from inbound transmissions

UART structure The Send/Receive buffers are FIFO buffers

UART Port Map - INPUT SysClk Std_Logic; Reset input Std_Logic; CS_N Std_Logic; RD_N Std_Logic; WR_N Std_Logic; RxD Std_Logic; Addr Std_Logic_Vector(1 downto 0); DataIn Std_Logic_Vector(7 downto 0);

UART Port Map - OUTPUT TxD Std_Logic; IntRx_N Std_Logic; IntTx_N Std_Logic; DataOut Std_Logic_Vector(7 downto 0)

UART 16550A Vs. UART 8250 The most commonly used UART is UART 16550A The main difference is the Send/Receive buffers – UART 8250 has 1 Byte – UART 16550A has 16 Byte – which makes it faster

RS-232 (Recommend Standard 232)

schedule * Learning VHDL DONE * Learning HDL Designer until 12/12 Model Sim Simplify Pro I.S.E Learning and implementation until midterm the core from “Open Cores” presentation

schedule Implementation until March 07