1 Chapter 13 Cores and Intellectual Property

2 Overview FPGA intellectual property (IP) can be defined as a reusable design block (Hard, Firm or soft) with a fixed-range of functionality Two primary potential benefits of IP use Reduced design schedule and design Reduced development cost and risk

3 Types of IP Three commonly recognized types of IP Soft IP Firm IP Hard IP Soft core: an HDL with no or minimal optimization for a specific target technology Firm core: an HDL that has been optimized for a specific target technology Hard core: design functionality implemented in fixed- logic at the gate and signal route level. The functionality cannot be removed or modified.

4 Categories of IP DSP function: Viterbi decoder, FFT, MAC, FIR, DCT Math function: Parallel Multiplier, Pipelined divider Base function: Shift register, Accumulator, Comparator, Adder Memory function: Block memory module, Distributed module Image processing: Color space converter, JPEG motion encoder Communication: AES compatible, Reed-Solomon encoder, Turbo decoder Microprocessor: UART, CRT controller, Wstcching timer Std. Bus Interface: LIN converter, PCI master/target, USB, I2C, CAN

5 Trade Studies IP trade-off analysis can be a challenging undertaking A key factor that relates to IP type selection is performance Another important factor: the amount and type of resource required to most efficiently implemented a complex function within an FPGA Flexibility is often a primary objective in FPGA design, and soft or firm implementations are generally the most flexible

6 Make versus Buy Evaluating factors The size and experience of the design team Design schedule and budget How much functionality must be implemented The decision to make or buy an IP begins by Developing a through understanding of required design functionality The functionality of available IP blocks

7 Sources of IP FPGA vendors Third-party IP supplies IP libraries associated with an FPGA design tool Open access groups Universities Internally developed

8 Evaluating IP Option To evaluate and test potential IP blocks IP codes can be most efficiently evaluated when they are implemented within the targeted FPGA device To understand that IP is generally not a seamless turn-key plug-in solution The quantity and quality of the design documentation

9 Qualifying an IP Vendor IP vendor qualification question checklist The level of deign pre-verification completed Availability of test benches and test results Supplier experiment with the targeted FPGA vendor/architecture component IP vendor tool set used to generate, synthesize, and simulate IP blocks IP design flow and testing procedures Meet the system-level requirements Additional detailed discussions with the IP suppliers regarding design details Identify and maintain a backup approach with one or more alternate vendors if possible

10 License, Tool, and Testing Licensing Issues License agreement with IP vendor, for each IP code Is the license project- or site-based? Can multiple versions of the same core be used on a project? Is multiple location support/implementation allowed? IP implementation/Tools IP testing/Debug

11 Q & A