Multiplexer as a Universal Function Generator

Slides:



Advertisements
Similar presentations
Basic Logic Gates Discussion D5.1 Section Sections 13-3, 13-4.
Advertisements

Logic Gates.
Lecture 5 EGRE 254 1/28/09. 2 Boolean algebra a.k.a. “switching algebra” –deals with Boolean values -- 0, 1 Positive-logic convention –analog voltages.
Combinational Logic Word Problems
Combinational Logic Circuits Chapter 2 Mano and Kime.
Morgan Kaufmann Publishers
111 Basic Circuit Elements n Standard TTL Small-Scale Integration: 1 chip = 2-8 gates n Requires numerous chips to build interesting circuits n Alternative:
Multiplexer as a Universal Function Generator Lecture L6.7 Section 6.2.
Decoders/DeMUXs CS370 – Spring Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of.
التصميم المنطقي Second Course
ECE 2373 Modern Digital System Design Exam 2. ECE 2372 Exam 2 Thursday March 5 You may use two 8 ½” x 11” pages of information, front and back, write.
Logic Design Fundamentals - 1 Lecture L1.1. Logic Design Fundamentals - 1 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.
Multiplexer as a Universal Element Discussion D2.6 Example 9.
Universal Gates Sum of Products Products of Sum
A Programmable Logic Device Lecture 4.3. A Programmable Logic Device Multiple-input Gates A 2-Input, 1-Output PLD.
Digital Electronics Dan Simon Cleveland State University ESC 120 Revised December 30, 2010.
Revision Mid 2 Prof. Sin-Min Lee Department of Computer Science.
Introduction to Computer Engineering by Richard E. Haskell Basic Logic Gates Module M1.1 Section 3.1.
ECE 301 – Digital Electronics Multiplexers and Demultiplexers (Lecture #12)
Combinational Logic Design Process
Combinational Logic Circuits Chapter 2 Mano and Kime.
Example of a Combinatorial Circuit: A Multiplexer (MUX)
Digital Logic Gates. Sum of Products (Review) Procedure: 1.Form a minterm for each combination of the variables that produces a 1 2.OR all the minterms.
2.7 NAND and NOR logic networks
1 Why study Boolean Algebra? 4 It is highly desirable to find the simplest circuit implementation (logic) with the smallest number of gates or wires. We.
Quiz What are the results of the following 4-bit bitwise logical operations? NOT OR NOR AND
EE2420 – Digital Logic Summer II 2013 Hassan Salamy Ingram School of Engineering Texas State University Set 4: Other Gates.
Digital Electronics Lecture 6 Combinational Logic Circuit Design.
1 CS151: Digital Design Chapters 4, 5 Review. CS Question 1 Design a combinational circuit for a Roller-Coaster ride in an amusement park. The design.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – Lab 6 Multiplexers,
Logic Gates. Outline  Logic Gates  The Inverter  The AND Gate  The OR Gate  The NAND Gate  The NOR Gate  The XOR Gate  The XNOR Gate  Drawing.
Sneha.  Gates Gates  Characteristics of gates Characteristics of gates  Basic Gates Basic Gates  AND Gate AND Gate  OR gate OR gate  NOT gate NOT.
Exclusive OR Gate. Logically, the exclusive OR (XOR) operation can be seen as either of the following operations:exclusive OR (XOR) 1. A AND NOT B OR.
Basic logic gates  AND gate:The truth table is given by A.BBA
Chapter 3 Gate-Level Minimization
Boolean Logic and Circuits ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.
1 EG 32 Digital Electronics Thought for the day You learn from your mistakes..... So make as many as you can and you will eventually know everything.
ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)
Chap 2. Combinational Logic Circuits
Chapter-3: BOOLEAN ALGEBRA & LOGIC GATES Analysis and logical design.
Logic Gates. AND gate Produces an output only if both inputs are on Input AInput BOutput (Q) Q=
Chapter 3 Digital Logic Structures
Appendix B: Digital Logic
NAND, NOR, and EXOR (more primitive logical gates) CS Computer Architecture David Mayer.
Mu.com.lec 9. Overview Gates, latches, memories and other logic components are used to design computer systems and their subsystems Good understanding.
Basic Gates and ICs 74LS00 Quad 2-Input NAND gate 74LS02 Quad 2-Input NOR gate 74LS04 Quad 2-Input NOT gate 74LS08 Quad 2-Input AND gate 74LS32 Quad 2-Input.
FIGURE 3.1 Two-variable K-map
Table 2.1 Postulates and Theorems of Boolean Algebra
Eng. Mai Z. Alyazji October, 2016
Computer Code.
ECE 3130 Digital Electronics and Design
DIGITAL LOGIC CIRCUITS
Exclusive OR Gate.
Part 4 Combinational Logic.
Computer Organization and Design Transistors & Logic - II
DIGITAL LOGIC CIRCUITS
Dr. Clincy Professor of CS
Boolean logic in CMOS.
UNIVERSAL GATES.
Universal gates.
Discrete Mathematics CS 2610
13 Digital Logic Circuits.
Homework 1 Due 21st May 2014.
Gates Type AND denoted by X.Y OR denoted by X + Y NOR denoted by X + Y
Table 2.1 Postulates and Theorems of Boolean Algebra
Boolean Algebra and Gate Networks
Eng. Ahmed M Bader El-Din October, 2018
Agenda Lecture Content: Combinatorial Circuits Boolean Algebras
Presentation transcript:

Multiplexer as a Universal Function Generator Discussion D4.3

Multiplexers s1 s0 C0 C1 4 x 1 MUX Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2

Multiplexers 1 s1 s0 4 x 1 MUX Y s1 s0 =XOR 0 0 C0 0 1 C1 1 1 0 C2 1 s1 s0 Y 1 =XOR C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 4 x 1 MUX Y C2 C3 s1 s0

Multiplexers 1 s1 s0 4 x 1 MUX Y s1 s0 =AND 0 0 C0 0 1 C1 1 0 C2 1 s1 s0 Y 1 =AND C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 4 x 1 MUX Y C2 C3 s1 s0

Multiplexers 1 s1 s0 4 x 1 MUX Y s1 s0 =OR 0 0 C0 0 1 C1 1 1 0 C2 1 s1 s0 Y 1 =OR C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 4 x 1 MUX Y C2 C3 s1 s0

Multiplexers 1 s1 s0 4 x 1 MUX Y s1 s0 =NAND 0 0 C0 1 0 1 C1 1 0 C2 s1 s0 Y 1 =NAND C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 4 x 1 MUX Y C2 C3 s1 s0

Multiplexers 1 Can you implement a logic circuit with s1 s0 Y 1 =NOR C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 4 x 1 MUX Y C2 C3 s1 s0 Can you implement a logic circuit with THREE inputs using a 4 x 1 MUX?

2 x 1 MUX is a universal element

Step 1 Implement the following logic equation using 2 x 1 MUXs f = xy' + xz + y'z x = 0 A = y'z x = 1 B = y' + z + y'z

Step 2 A = y'z y = 0 0-input = z y = 1 1-input = 0 B = y' + z + y'z

4 x 1 MUX f = xy' + xz + y'z The variable f is 1 if x > y or if x = y and z = 1.

Majority Circuit C0 C1 4 x 1 MUX Y C2 s0 C3 s0 s2 s1 1