DAQ for KEK beam test M.Yoshida (Osaka Univ.)

Components VLPC readout –Stand Alone Sequencer (SASeq) Slow < 100Hz –Buffering VLPC data with VME interface Fast > 10kHz expected TOF counter readout –CAMAC ADC/TDC in KEK elec. Pool –Readout via VME with VME-CCP interface module CCP : max 10 MByte/sec DAQ software –UniDAQ developed by KEK –Running on Linux –Server (Evbuilder) + Clients (Collectors) –Already installed in PC at D0 test stand –Need to write collectors EvBuilder VLPC Collector TOF Collector The other Detectors ethernet VME CAMAC TKO?

VLPC backplane Linux PC PCI-VME SASeq #2 SASeq # LVDS-VME # ３ LVDS-VME # ４ AFE II (L) AFE II (R) VLPC Cassette #2 VLPC Cryostat AFE II (L) AFE II (R) VLPC Cassette #1 VME BUS System Overview CAMAC-VME CAMAC crate 6U Serialized ADC DATA Slow Control AFE II Control 1024 ch 8x64 ch 4x8bit = 32 bit / board 8x64 ch LVDS-VME #1 LVDS-VME # ２

LVDS  VME MCM puts serialized ADC data –Need to deserialize before FIFO Solution 1: –Custom-made VME board [MCM  serialize]  cable  [deserialize  FIFO]  VMEbus –Under development in Fermilab Solution 2: –Use KEK-FIFO board 32-bit inputs / board [MCM  serialize]  cable  [deserialize]  cable  [FIFO board]  VMEbus –Under development decoder board to deserialize ADC data

D0 FIFO board Newly-designed by fermilab Need to design –VME interface –FPGA program FPGA FIFO/SRAM VME interface VME bus 3:21 LVDS receiver (66MHz) SN65LVDS p metric conn. AMP

KEK FIFO board (GNV-100) Already exist / debugged Standard VME 6U module NIM ext. clock input NIM trigger input TTL 2x 16 bit data input Operation in 100MHz Depth: 65K x 32 bits –FIFO: IDT72V36100 Need LVDS decoder

CN-34P D10-D17 A0-A2 D0-D7 CN-34P D10-D17 D0-D7 RJ-48 3:21 LVDS receiver (66MHz) SN65LVDS96 DS90CR216A CLKOUT NIM CLOCK OUT CLKOUT NIM CLOCK OUT LVDS-TTL module (deserialize) Need +5/-5V power supply –Standard VME 6U board 2x 8-pin deferential LVDS inputs 2x 16 bit TTL outputs NIM clock out CLKIN A0-A2 CLKIN

Summary Started to design DAQ system for KEK beam test in the summer of 2005 Buffer module for VLPC data is under development to increase DAQ rate up to 10 kHz –D0 FIFO module –KEK FIFO module + decoder board DAQ test / preparation in Nov. and Dec. –The completed system will be sent to KEK