Kameshwar Poolla Mechanical Engineering Electrical Engineering & CS University of California, Berkeley April 10, 2006 Wireless Metrology and Process Control for Semiconductor Manufacturing This research was supported by NSF, UC SMART, & gifts from Intel, AMD, Novellus, Applied Materials, Cypress, Lam Research, TEL, Nikon.

6/27/20152 semiconductormanufacturingbackground

slide 3 What is it? Selective deposition & selective removal of various materials to form ICs Selectivity is done by protecting desired areas with resist IBM Power PC750

6/27/2015 slide 4 Lithography Start with a Si waferSpin-coat ResistCr MaskExposePost Exposure Bake DevelopEtch or Deposit

6/27/2015 slide 5 Process Overview Resist PAB Scanner Develop Production Wafer Flow PEB PDB Etch Track Photomask

6/27/2015 slide 6 Critical Dimension (CD) Captures quality of pattern transfer CD Target – desired width of printed lines CD(x,y) – actual width of printed lines Depends on (x,y) because process varies across wafer Measured on test wafers using CD SEM or Scatterometry

6/27/2015 slide 7 CD means μ and spreads σ Want CD Mean at Target small CD means  faster switching speeds CD spread Across wafer & wafer-to-wafer small CD spread  can use aggressivedesign rules  higher device density  better binning yields

6/27/2015 slide 8 Good Bad

6/27/2015 slide 9 Yield Binning Post OnWafer Optimization 6nm Bin 2 Bin 3 Device/Fab Economics Bin 1 $ Intel P4 Prices: 3.8 GHz - $ GHz - $ GHz - $279 Typical CD Distribution 11nm Target CD Improved Yield & Bin Sort = $$$ Yield

6/27/2015 slide 10 Post Exposure Bake Key step – greatly influences CD μ and  Makes exposed resist diffuse To reduce standing wave patterns Gives better pattern transfer Must be very accurately controlled State-of-the-art ±0.3 ºC across 300 mm wafer

6/27/2015 slide 11 PEB reduces Standing Waves Courtesy of CNF, Cornell University

6/27/2015 slide 12 Our Plan ~1997 Decided to do Control of Lithography Feedback Control requires Sensors & Actuators Available Actuation? Plenty – exposure dose, focal plane, PEB Temp Available Sensors in Lithography? Not many and pretty useless for control

6/27/2015 slide 13 Need in situ Sensing What was the state of the wafer during processing? processing equipment wafers to be processed finished wafer

6/27/2015 slide 14 in situ Sensing Need wafer-state information –Temperature in post-exposure bake –Latent image in lithographic exposure –Etch rate of wafer in plasma etch –Deposition rate in CVD processes The Big Problems –Chamber access –Deployment cost

6/27/2015 slide 15 In-situ sensor array with integrated power and telemetry Solution: SensorWafers

6/27/2015 slide 16 feedback process control processing equipment data SensorWafer base station The Approach wafers to be processed

6/27/2015 slide 17 Temperature Sensors Useful for PEB, plasma etch, implant Objectives Monitor wafer temperature at 4 locations (within 1ºC) Design –Off-the-shelf temperature sensor modules –PIC microprocessor (with integrated 4 channel A/D) –Infrared data transfer (IrDA compliant) –Error detection (CRC-16 )

6/27/2015 slide 18 Early attempts … Ir-LED PP Batteries Sensor Ir-LED PP Batteries Sensor Problems: clearance, isolation, contamination & they are ugly !

6/27/2015 slide 19 Etch Rate Sensor Sensor to measure polysilicon etch rate Based on van der Pauw probe electrical film- thickness measurement : I I Poly-Si V

6/27/2015 slide 20 Design # 1

6/27/2015 slide 21 The effect of Temperature

6/27/2015 slide 22 Results Problems: clearance, isolation, contamination

6/27/2015 slide 23 Thermal Flux Sensors Plasma etch is highly sensitive to wafer temp etch rate, selectivity, and anisotropy Heat delivered to the wafer has two sources –Ion flux bombardment Indirect measure of physical etch –Exothermic chemical etch reactions Indirect measure of chemical etch Want to resolve these heat fluxes –Can deduce sidewall, anisotropy etc.

6/27/2015 slide 24 Heat flux sensor design Simple, layered heat flux gauge Not enough sensitivity Dielectric, thermal conductivity  Temperature Sensors t Incident heat flux (q  )

6/27/2015 slide 25 Make the Heat Travel Far Incident heat flux Antenna Base Membrane TT

6/27/2015 slide 26 Membrane Top View D Membrane Side View Heat flow within thin dielectric membrane TT Antenna / Membrane Structure b TT Heat sink Heat sink Heat flow Incident heat

6/27/2015 slide 27 Discrimination between physical and chemical sources Use two heat flux sensors: one exposed, one covered –Exposed sensor is heated by both sources –Covered sensor receives only physical heating Heat Flux Resolution

6/27/2015 slide 28 Membrane: Silicon nitride Antenna: SiO 2 / Aluminum Plasma-etched material: resist (O 2 plasma) Temperature sensors: polysilicon Tethered power and communication Design #1 Heat sink Si Al PR SiO 2 Si 3 N 4 poly

6/27/2015 slide 29 Layout – Wheatstone Bridge Etched SensorNon-Etched

6/27/2015 slide 30 Layout – Full Die (20 per wafer) Edgeboard Connector Sensors

6/27/2015 slide 31 Antenna: Undoped polysilicon (low  ) Linewidths: increased Tethered power and communication Design # 2 Heat sink Si PR poly Si 3 N 4 poly

6/27/2015 slide 32 Final Design

6/27/2015 slide 33 Testing Test sensors on the “bench” –Use an off-the-shelf heat flux sensor and a heating element to compare readings: Aluminum heat sink off-the-shelf sensor sensor heater vacuum chamber

6/27/2015 slide 34 Bench-top Results

6/27/2015 slide 35 Going up the food chain Sensors become rapidly commodified Value is in using the data This is through Control, Modeling, Optimization Examples –Equipment Control –Fault Detection and Isolation –Process Optimization

6/27/2015 slide 36 The Value of Control PEB Example Control spatial temperature of bake plate Yesterday ± 0.3 °C Today ± 0.15 °C Result: 1 nm reduction in CD spread Benefit: mid-sized fab in 1 st year of product lifecycle ~$3/die * 200 die/wafer * 20,000 wafer/mon * 12 mon/yr 144 M$ per year !!