abk C.A.D. Agenda u Roadmapping: “Living Roadmaps” for systems u SiP physical implementation platforms (CLC, SOS) s Tools needs u Interfaces and standards (“infrastructure”) for design process s Internal to flows and methodologies s External: down (manufacturing variability models, mask flow handoff, cluster tool abstractions, … ) or up (IO cells, signaling standards, logic, system-level, …) s Reusable, composable solvers  rapid flow synthesis/optimization s Measurement and quantification of design quality, design productivity s Concrete realizations of GSRC and other methodologies t with metrics and automated evaluators (bX)

abk Infrastructure and Benchmarking Agenda u Today 9:00 – 10:00 s BX and Benchmarking Status s Saurabh Adya: new Placement Utilities slot s Aaron Ng: Creating a Living Benchmarking Resource Using BX u Today 10:00 – 11:00 s Placement-Centered Directions (Mini-Flows, New Problems) s Xiaojian Yang: Industry suggestions u Today 11:00 – 12:30 pm s Concrete steps with OpenAccess s Mark Bales: OA status update s Discussion

abk Placement-Centered Open Problems u Incremental Placement u Combined Placement and Floorplanning s locks solution into a bad subspace s Timing is a constraint (not an objective); WL is an objective s Problem = lack of understanding of interrelationships between different objectives, e.g., timing, area (fixed-die) and congestion t N.B.: WL may not really be an objective: it is a proxy for congestion (area) s Issue of capturing timing in top-down partitioning-based placement (partitioning is net-based; timing is path-based) u Open question: How is SI solved at placement? u IR drop placement? u Variability-aware placement?

abk u Thermal placement (not just dynamic power minimization) s Given activities of all gates, find a placement to minimize a linear combination of dynamic power and maximum thermal variation u Hierarchy-driven placement? s Probably moving to flat, so this seems less important u Datapath-based (timing-constrained) placement s People have tried but have not achieved notably better results s 2 literature from late 1980’s: Ebeling et al. subgraph isomorphism, Odawara/Szymanski/Nijssen-Jess/Varadarajan-Arikati on regularity extraction Placement-Centered Open Problems

abk u Power implications (voltage islands) s Chuck also mentions this s Clock gating s Multi-Vdd islands: granularity of several hundred cells (?) – 1-2 rows min in V, stripe pitch min in H s Ground islands (shutdown of blocks keeping memory partially powered up) s Cf. Amir’s work at Northwestern ~1995 u Placement for BIST (check with Tim Cheng et al.) u Signal Integrity Issues (crosstalk handling at floorplan and placement) u Clock distribution u ABK Suggestion: Single-width, single-pitch cell layout, synthesis, place and route flow: WOULD BE HEROES !!! (PhasePhirst!, SCAAM, etc. == next-generation lithography proposals, all of which depend on “hyper- resolution” (“2-beam imaging”)  basically, only one direction and one pitch will print (the layout is a subset of a grating). Goal: C.A.D. people should prove a one-time, bounded hit on Moore’s Law (e.g., 30% density) but then scalability of SP&R thereafter. Placement-Centered Open Problems

abk u X, Y Architectures March 5 th EE Design ? u Design for Variability u Backend Process Optimization s Complex objective: marketing, methodology, integration s Marketing: BEOL should be optimized for many designs (derivatives, etc.) – range of size, frequency, etc. s Methodology: Crosstalk, IR drop, routing density, etc. t Statistical information : %WL per layer, %designs having X #gates, Y MHz, s Integration: cost of fabrication (e.g., AR limits, low metal-layer count, #layers, thickness (mfg throughput, pitch LBs from AR limits, …)) Placement-Centered Open Problems