1 Lucas-Lehmer Primality Tester Presentation 11 April 24th 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: Modular Arithmetic unit with a creative use

2 Status Finished –Project Chosen –C simulations –Behavioral Verilog –Structural Verilog –Floor Plan –Schematics –Pathmill Simulation of Top Level –Module Layout –Global Layout In Progress –Global Simulations

3 Final Floorplan

4 Floorplan

5 Poly Layer Mask

6 Metal1 Layer Mask

7 Metal2 Layer Mask

8 Metal3 Layer Mask

9 Metal4 Layer Mask

10 compare Propagation Delay

11 partial_product Propagation Delay

12 Propagation Delays ModuleSchematicextractedRC FSM80ps270ps mod_p769ps944ps mod_add817ps907ps partial_product -shift_left -shift_right -sub_ ns 780ps 779ps 144ps - 964ps 976ps 167ps count645ps954ps compare727ps2.25ns

13 Power Estimates ModuleSchematicextractedRC FSM8.88uW11.72uW mod_p60.63uW77.80uW mod_add86.16uW89.75uW partial_product368uW- count53.81uW60.35uW compare131.1nW1.98uW

14 Design Specifications ModuleTransistor Count Area (µm²) Transistor Density FSM1521, mod_p1,2808, mod_add1,1685, partial_product7,32854, count1,4128, sub_165762, Registers8966, compare Total12,85286, Aspect Ratio

15 What’s Next Simulations on Global Design

16 Questions?