S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 21: Differential Circuits and Sense Amplifiers Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07 Remember Cascode Voltage Switch Logic Cascode voltage Switch logic Adv: no static power dissipation compared to pseudo-NMOS radioed circuits differential signaling Disadv: potentially large diffusion capacitance (slowing things down) How can we cut down the diffusion capacitance?

S. Reda EN160 SP’07 Differential Split-Level Circuits Adv: The reference voltage (V DD /2+V t ) limits the swing on the internal diffusion nodes (X) to 0-V DD /2  reduces parasitic delay Disadv: Introduces series resistance does not help the delay much Brings static power back into the picture

S. Reda EN160 SP’07 Sense Amplifiers Function:  Senses small differential input signals and magnify them into larger out signals  reduces delay  Commonly used in memory in which differential bit lines have huge capacitances

S. Reda EN160 SP’07 Sense Amplifiers

S. Reda EN160 SP’07 Sample Set Differential Logic (SSDL) During sample, when Ф is low: Both the precharge and evaluation transistors are ON  static current consumed One of the internal nodes (X or Xbar) is precharged high; contention on the other During set, when Ф is high: Precharge and evaluation transistors are OFF Sense amplifier turns on pulling the lower of the two nodes to the ground

S. Reda EN160 SP’07 Enable/Disable CMOS Differential Logic When Ф is high both outputs are pulled low pull-up stack is turned off (no static power) When Ф is low output gate is enabled one output will be held high, the other pulled down sense-amp uses positive feedback to produce a faster swing The sense amplified uses cross-coupled inverters

S. Reda EN160 SP’07 Summary Done with chapter 6 (Combinational Circuit Design). Ignore Section 6.7 (Silicon-on- Insulator) Next time: material review for the exam (or better on Monday?)