ICCAD’01: November, 2001 Instruction Generation for Hybrid Reconfigurable Systems Ryan Kastner, Seda Ogrenci-Memik, Elaheh Bozorgzadeh and Majid Sarrafzadeh Ryan Kastner, Seda Ogrenci-Memik, Elaheh Bozorgzadeh and Majid Sarrafzadeh Embedded and Reconfigurable Systems Group Computer Science Department UCLA Los Angeles, CA Embedded and Reconfigurable Systems Group Computer Science Department UCLA Los Angeles, CA 90095

ICCAD’01: November, 2001OutlineOutline Introduction Programmability Hybrid Reconfigurable Systems Strategically Programmable System Instruction Generation Uses in Hybrid Reconfigurable Systems Relation to Template Generation and Matching Algorithm for Template Generation and Matching Experiments Conclusion Introduction Programmability Hybrid Reconfigurable Systems Strategically Programmable System Instruction Generation Uses in Hybrid Reconfigurable Systems Relation to Template Generation and Matching Algorithm for Template Generation and Matching Experiments Conclusion

ICCAD’01: November, 2001ProgrammabilityProgrammability Future systems need programmability multiple levels of computation hierarchy Computational Hierarchy: Future systems need programmability multiple levels of computation hierarchy Computational Hierarchy: Gate Level ADD Register MUL Control  -Architecture Level FU Memory Register Bank Control ArchitectureLevel FUProgrammabilityBitByteInstruction (8 – 128 bits) Basic Unit of Computation Boolean Operation (and, or, xor) Arithmetic Operation Functional Operation Communication Direct wires connections Bundles of wires, registers Bus, memory Hybrid Reconfigurable Systems have programmability at one or more levels Register

ICCAD’01: November, 2001TradeoffsTradeoffs ADD Register MUL Control FU Memory Register Bank Control FU Register Example Platform Types of Programmable Units Custom instructions, Register banks Datapath unit, Control unit, RAM CLBs, LUTs Architecture level Micro- architecture level Gate level Hybrid Reconfigurable Systems should find a happy medium Tensilica, Improv Chameleon Systems Xilinx, Altera Flexibility Configuration Time Thousands of cycles Hundreds of cycles

ICCAD’01: November, 2001 SPS - Strategically Programmable System Embed (hard or soft) computational units – Versatile Programmable Blocks (VPB) - into FPGA-like fabric Combine programmable units from gate, microarchitecture and architecture levels Balance flexibility and configuration time Embed (hard or soft) computational units – Versatile Programmable Blocks (VPB) - into FPGA-like fabric Combine programmable units from gate, microarchitecture and architecture levels Balance flexibility and configuration time VPB Memory Need automated method of determining the functionality of VPBs

ICCAD’01: November, 2001 SPS Architecture RoutingArch. Overview of SPS SPS Compiler SPS Architecture Generation VPBSynthesis SPSModulePlacement Set of applications specified in high level code (c/c++, fortran, MOC) Compile to low Compile to low level specification level specification Determine VPB Determine VPB functionality functionality

ICCAD’01: November, 2001 VPB Instruction Generation Given a set of applications, what computation should be implemented on VPBs? RAM VPB VPBs? Want complex, commonly occurring computation patterns Look for computational patterns at the instruction level Basic operation is add, multiply, shift, etc. Want complex, commonly occurring computation patterns Look for computational patterns at the instruction level Basic operation is add, multiply, shift, etc. Set of applications VPB RAM

ICCAD’01: November, 2001 Problem Definition Determining VPB functionality requires regularity extraction Regularity Extraction - find common sub-structures (templates) in one or a collection of graphs Each application can be specified by collection of graphs (CDFGs) Templates are implemented as VPBs Two related sub-problems: Template Matching Template Generation Determining VPB functionality requires regularity extraction Regularity Extraction - find common sub-structures (templates) in one or a collection of graphs Each application can be specified by collection of graphs (CDFGs) Templates are implemented as VPBs Two related sub-problems: Template Matching Template Generation

ICCAD’01: November, 2001 Template Matching – Formal Def’n Problem 1: Given a directed, labeled graph G(N, A), a library of templates, each of which is a directed labeled graph T i (V,E), find every subgraph of G that is isomorphic to any T i + * * + + *+ + *& + || + + & ** Templates T +* *+ + & %+ + % ** *&|| **+ ++ Directed Labeled Graph G T1T1 T2T2 T3T3 T4T4 T5T5 T6T6

ICCAD’01: November, 2001 Template Matching – Formal Def’n Problem 2: Given an infinite number of each set of templates  = T 1, …, T k and an overlapping set of subgraphs of the given graph G(N,E) which are isomorphic to some member of  ; minimize k as well as  x i where x i is the number of templates of type T i used such that the number of nodes left uncovered is the minimum. +* *+ + & %+ + % +* *&|| **+ ++

ICCAD’01: November, 2001 Template Generation Templates may not always be given as input An automatic regularity extraction algorithm must develop it’s own templates Generate a set of templates such that: Number of templates is minimized Covering of the graph is maximized Templates may not always be given as input An automatic regularity extraction algorithm must develop it’s own templates Generate a set of templates such that: Number of templates is minimized Covering of the graph is maximized

ICCAD’01: November, 2001 Related Work Useful in a wide variety of CAD applications Data path regularity [Chowdhary98], [Callahan99] Scheduling [Ly95] System partitioning [Rao93] Low power design [Mehra96] Soft macros – CPR [Cadambi99] for PipeRench architecture Useful in a wide variety of CAD applications Data path regularity [Chowdhary98], [Callahan99] Scheduling [Ly95] System partitioning [Rao93] Low power design [Mehra96] Soft macros – CPR [Cadambi99] for PipeRench architecture

ICCAD’01: November, 2001 An Algorithm for Simultaneous Template Generation and Matching 1. Given a labeled digraph G(V, E) 2. # C is a set of edge types 3. C   4.while (stop_conditions_not_met(G)) 5. C  profile_graph(G) 6. cluster_common_edges(G, C) 1.Find the most common edge type 2.Contract common edges 3.Repeat until stopping condition met Formal Definition Informal Definition

ICCAD’01: November, 2001 Explanation of Algorithm Edge contraction: Merge adjacent nodes and maintain connectivity Stopping Conditions Reach certain number of templates Graph sufficiently covered No frequently occurring edge type Stopping Conditions Reach certain number of templates Graph sufficiently covered No frequently occurring edge type Profile Edges: Find most common edge types ContractEdge + * * * * + * * * * + * * * * * * Most Common Edge Type

ICCAD’01: November, 2001 Edge 1 Edge 2 Edge 3 Edge 4 Algorithm in Action *** ** >>% * & + Iteration 2 *** ** >>% * & + MIS Edge 2 Conflict Graph Edge 1 Edge 3 Edge 4 Create Conflict Graph Determine MIS *** ** >>% * & + Contract edges 2 and 4 Templates *** ** >>% * & + Contract edges Templates

ICCAD’01: November, 2001 Algorithm Summary Algorithm can be generalized and used in a variety of applications Easily extended to hypergraphs Input/output pin restrictions can easily be added Performs template generation and matching simultaneously Algorithm can be generalized and used in a variety of applications Easily extended to hypergraphs Input/output pin restrictions can easily be added Performs template generation and matching simultaneously We target algorithm towards VPB generation in SPS

ICCAD’01: November, 2001 Experimental Setup Set of applications specified in C SUIF&Machine-SUIF Control Flow Graph + * + * + Control Dataflow Graph DataflowGraphGenerationPass

ICCAD’01: November, 2001 PerformTemplateGeneration and Matching Experimental Setup MediaBench Files + * + * + Control Dataflow Graph Compile to CDFGs GatherStatistics: Graph Coverage, Num. Templates

ICCAD’01: November, 2001 BenchmarkC FileDescription mpeg2motion.cMotion vector decoding mpeg2getblk.cDCT block decoding adpcmadpcm.cADPCM to/from 16-bit PCM epicconvolve.c2D general image convolution jpegjctrans.cTranscoding compression jpegjdmerge.cColor conversion rastafft.cFast Fourier Transform rastanoise_est.cNoise estimation functions gsmgsm_decode.cGSM decoding gsmgsm_encode.cGSM encoding Experimental Setup - Benchmarks Selected files from MediaBench

ICCAD’01: November, 2001 Similarity Across Applications Oper- ation MediaBench file name motionjdmergegetblkgsm_decjctrans ADD50.3%84.6%44.5%29.6%84.6% MUL36.3%13.8%24.0%22.4%13. 8% Template Coverage MUL- MUL 0.0% 1.3%0.0% ADD- ADD 14.5%9.1%3.2%3.6%9.1% ADD- MUL 0.0%0.4%0.6%0.0%0.4% MUL- ADD 36.3%13.0%21.5%22.4%13.0%

ICCAD’01: November, 2001 Experimental Results Techniques Simple – restrict templates to two operations No restrictions – unlimited amount of operations Stopping condition: most common edge occurs < x% (x  5-25) Techniques Simple – restrict templates to two operations No restrictions – unlimited amount of operations Stopping condition: most common edge occurs < x% (x  5-25)

ICCAD’01: November, 2001SummarySummary Systems need programmability at multiple levels of the computational hierarchy Introduced SPS as a Hybrid Reconfigurable System Developed an instruction generation algorithm to determine VPB functionality Showed that common templates can be found across a similar set of applications An efficient covering possible using simple templates Future work: Create methods to uncover more complex templates Systems need programmability at multiple levels of the computational hierarchy Introduced SPS as a Hybrid Reconfigurable System Developed an instruction generation algorithm to determine VPB functionality Showed that common templates can be found across a similar set of applications An efficient covering possible using simple templates Future work: Create methods to uncover more complex templates