Soha Hassoun Tufts University Medford, MA Thanks to: Carl Ebeling University of Washington Seattle, WA Fine Grain Incremental Rescheduling Via Architectural Retiming

RAM Offset Example Problem -- Clock period is too large Write Address Read Address

RAM Write Address Read Address Offset Pipelining Problems w/ consecutive dependent operations

Performance Bottleneck Latency constrained paths Latency constrained paths Latency = n

Performance Bottleneck Latency constrained paths Latency constrained paths Latency = n Approach Approach apply architectural retiming at the RT level

Problem: too much work, too little time Architectural Retiming ykyk

Problem: too much work, too little time D pipelineregister ykyk Architectural Retiming

N negative register Problem: too much work, too little time pipelineregister D C ykyk Architectural Retiming

N negative register Problem: too much work, too little time pipelineregister D C ykyk Architectural Retiming precomputation prediction

Outline Precomputation Precomputation incremental rescheduling without resource constraints incremental rescheduling without resource constraints Prediction Prediction incremental rescheduling with resource constraints incremental rescheduling with resource constraints Results Results

D t = C t+1 Precomputation Function h h h D C xixi f f g g ykyk x´x´ i N

D t = C t+1 = f (..., x i t+1,... ) = f (..., x i t+1,... ) Precomputation Function h h h D C xixi f f g g ykyk x´x´ i N

D t = C t+1 = f (..., x i t+1,... ) = f (..., x i t+1,... ) x i t+1 = x´ i t = g (..., y k t,... ) Precomputation Function h h h D C xixi f f g g ykyk x´x´ i N

f´ D t = C t+1 = f (..., x i t+1,... ) = f (..., x i t+1,... ) x i t+1 = x´ i t = g (..., y k t,... ) Precomputation Function h h h D C xixi f f g g ykyk x´x´ i N D t = f (..., g (..., y k t,... ),...) = f´(..., y k t,... ) = f´(..., y k t,... )

Incremental Rescheduling h h h f f g g ykyk Time n g Time n+1 f, h N

f´ Incremental Rescheduling h h h f f g g ykyk Time n g Time n+1 f, h N Time n f ’ Time n+1 h

Precomputing With Register Arrays Read Data Write Address Read Address Write Data Read Data

Precomputing With Register Arrays Write Address Read Address Write Data Read Data Out N F

Precomputing With Register Arrays F t = Out t+1 Write Address Read Address Write Data Read Data Out N F

Precomputing With Register Arrays F t = Out t+1 = Array t+1 [Read Address t+1 ] Write Address Read Address Write Data Read Data Out N F

Synthesizing Bypass Paths Write Address Precomputed Read Address Write Data Read Data = ? Write Address Read Address Write Data Read Data

Precomputing RAM Output RAM N

Prediction D C f f gigi Z N What if ? What if ? can’t precompute, can’t precompute, too many additional resources, or too many additional resources, or performance is unsatisfactory performance is unsatisfactory

Prediction D C f f gigi Z N What if ? What if ? can’t precompute, can’t precompute, too many additional resources, or too many additional resources, or performance is unsatisfactory performance is unsatisfactory Predict C one cycle before its arrival Predict C one cycle before its arrival

Schedule with Mispredictions C H R1R2 t-1 t t+1 C c1c2 H h1h2 

Schedule with Mispredictions C H R1R2 t-1 t t+1 C c1 H  Verify Negative Register c2 h1h2

Schedule with Mispredictions C H R1R2 t-1 t t+1 C c1 H  Verify Negative Register

Schedule with Mispredictions C H R1R2 t-1 t t+1 C c1 H  h1 c1*=? c1 c1* Verify Negative Register c2* c2 h2 c2*=? c2 c2

Synthesis Issues in Prediction Negative register as predicting FSM Negative register as predicting FSM use signal transition probabilities use signal transition probabilities incorporate don’t care conditions incorporate don’t care conditions Nullifying mispredictions Nullifying mispredictions Two correction strategies Two correction strategies As-Soon-As-Possible restoration As-Late-As-Possible correction Add handshaking signals to coordinate with interface Add handshaking signals to coordinate with interface

Related Work Precomputation Precomputation Bypass Synthesis Bypass Synthesis lookahead [Kogge ‘81, …..] lookahead [Kogge ‘81, …..] Prediction / Speculative Execution Prediction / Speculative Execution Most likely path, arbitrarily deep [Holtmann & Ernst ‘93,’95] Most likely path, arbitrarily deep [Holtmann & Ernst ‘93,’95] Pre-execution [Radivojevic & Brewer ‘94] Pre-execution [Radivojevic & Brewer ‘94] Possible multiple paths & arbitrarily deep [Lakshminarayana et al. ‘98] Possible multiple paths & arbitrarily deep [Lakshminarayana et al. ‘98] Percolation scheduling [Potasman et al. ‘90] Percolation scheduling [Potasman et al. ‘90]

Results

Architectural Retiming Improves throughput while preserving functionality and sometimes latency Improves throughput while preserving functionality and sometimes latency Bridge gap between HLS and logic optimizations Bridge gap between HLS and logic optimizations Unifies several sequential optimizations Unifies several sequential optimizations bypass synthesis bypass synthesis lookahead transformation lookahead transformation branch prediction branch prediction fine-grain cross register optimizations fine-grain cross register optimizations

Ph.D. Forum at DAC ‘99 Goal Goal increase interaction between academia and industry increase interaction between academia and industry Format Format students present work at poster session at DAC students present work at poster session at DAC researchers give feedback researchers give feedback Who’s eligible? Who’s eligible? Students within 1 or 2 years of finishing Ph.D. thesis Students within 1 or 2 years of finishing Ph.D. thesis

The End

Precomputing in Single-Register Cycles Original Circuit BA

Precomputing in Single-Register Cycles Original Circuit N BA

Precomputing in Single-Register Cycles Lookahead -- A(n) is a function of B(n-2) N BA A' BA B' [Kogge, ‘81], [Parhi & Messerschmidtt, ‘89]

Precomputing RAM Output RAM

Precomputing RAM Output RAM

Speculative Execution c1 c2 c3 c4 c5 c6 Scope and Depth

Speculative Execution Scope and Depth