CS 140 Lecture 18 Professor CK Cheng 12/3/02. Standard Sequential Modules 1.Register 2.Shift Register 3.Counter.

Slides:

Advertisements

Similar presentations

Modulo-N Counters Module M10.4 Section 7.2.

Advertisements

By: Masud-ul-Hasan Experiment 8 How will be the shift registers used here?

Lecture 23: Registers and Counters (2)

Shift Registers Module M11.1 Section 7.3.

1 CS 140L Lecture 8 System Design Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 10 Sequential Networks: Implementation Professor CK Cheng CSE Dept. UC San Diego 1.

Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.

CS 140L Lecture 5 Professor CK Cheng CSE Dept. UC San Diego.

CS 140L Lecture 5 Professor CK Cheng 4/29/02. Asynchronous Counter D Q CLK D Q D Q There are n flip-flops. D FF is the delay of each flip-flop. When n.

CS 140 Lecture 17 Professor CK Cheng 11/26/02. System Designs 1.Intro 2.Spec 3.Implementation.

CS 140 Lecture 7 Professor CK Cheng 4/23/02. Part II. Sequential Network (Ch ) 1.Flip-flops SR, D, T, JK, 2.SpecificationState Table 3.Implementation.

CS 140 Lecture 9 Professor CK Cheng 4/30/02. Part II. Sequential Network 1.Memory 2.Specification 3.Implementation S XY s i t+1 = g i (S t, x t )

CS 140 Lecture 11 Professor CK Cheng 5/09/02. Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder,

1 CS 140 Lecture 19 Sequential Modules Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 8 Professor CK Cheng 4/26/02. Part II. Sequential Network 1.Memory SR, D, T, JK, 2.Specification S XY s i t+1 = g i (S t, X t )

Sequential Logic Design

CS 140L Lecture 5: Counters Professor CK Cheng CSE Dept. UC San Diego 1.

Digital Circuit Review: Combinational Logic Logic operation –Need to know following two input gates: NAND, AND, OR, NOT, XOR –Need to know DeMorgan’s Theorems.

CSE 140L Lecture 4 Flip-Flops, Shifters and Counters Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 13 Combinational Standard Modules Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140 Lecture 17 System Designs III Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140 Lecture 18 Professor CK Cheng 6/04/02. Part IV. System Designs Algorithm: { Input X, Y type bit-vector, start type boolean; Local-Object A, B type.

CS 140 Lecture 12 Professor CK Cheng 11/07/02. Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder,

CS 140 Lecture 14 Professor CK Cheng 11/14/02. Part II. Standard Modules A.Interconnect B.Operators. Adders Multiplier Adders1. Representation of numbers.

Sequential Logic Design

CS 140 Lecture 10 Professor CK Cheng 5/02/02. Given the state table, implement with 2 JK flip flops id Q 1 (t) 0 1 Q 0 (t) X(t)

Shift Registers Lecture L6.6 Section Bit Shift Register.

Lecture 1: Introduction to Digital Logic Design CK Cheng Tuesday 4/1/02.

Sequential PLD timing Registers Counters Shift registers

CS 140 Lecture 10 Professor CK Cheng 10/29/02. Part II. Sequential NetworkReminder 1.Flip flops 2.Specification 3.Implement Netlist  State Table  State.

CS 140 Lecture 8 Professor CK Cheng 10/22/02. Part II. Sequential Network 1.Flip-flops SR, D, T, JK, State Table Characteristic Eq. Q(t+1) = f(x(t), Q(t)).

CS 140L Lecture 7 Transformation between Mealy and Moore Machines Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 19 Professor CK Cheng 12/05/02. Sequential Machine Standard Modules Combinational Sequential System Designs.

CS 140 Lecture 9 Professor CK Cheng 10/24/02. Sequential Network 1.Components F-Fs 2.Specification D Q Q’ CLK.

CSE 140 Lecture 15 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140L Lecture 4 Professor CK Cheng 10/22/02. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

Design of Counters ..

Digital Components Dr. Voicu Groza SITE Hall, Room ext. 2159

Princess Sumaya Univ. Computer Engineering Dept. Chapter 6:

EE365 Adv. Digital Circuit Design Clarkson University Lecture #12 Registers and Counters.

Counters. November 5, 2003 Introduction: Counters  Counters are circuits that cycle through a specified number of states.  Two types of counters: 

1 Registers & Counters Logic and Digital System Design - CS 303 Erkay Savaş Sabancı University.

Digital Fundamentals Tenth Edition Floyd Chapter 9.

Digital Electronics.

EE121 John Wakerly Lecture #9

CSE 140 Lecture 15 System Design II CK Cheng CSE Dept. UC San Diego 1.

Shift Register Counters

CSE 140 Lecture 13 System Designs

CSE 140 Lecture 14 System Designs

CSE 140 Lecture 14 System Designs

Prof. Hsien-Hsin Sean Lee

Sequential Logic Counters and Registers

CSE 140 Lecture 16 System Designs

CSE 140 Lecture 15 System Designs

Shift Registers Lecture L8.6 Section 8.3.

CSE 140 Lecture 17 System Design II

Analog-to-Digital Converters

CS 140 Lecture 16 Professor CK Cheng 11/21/02.

CSE 140 Lecture 14 System Design

CS 140 Lecture 19 Standard Modules

CS 140 Lecture 15 Sequential Modules

CSE 140 Lecture 16 System Designs II

CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 16 March 14 W’05 Yutao He 4532B Boelter Hall

Switching Theory and Logic Design Chapter 5:

14 Digital Systems.

CSE 140 Lecture 9 Sequential Networks

CS 140 Lecture 13 Professor CK Cheng 11/12/02.

CS 140L Lecture 8 Professor CK Cheng 11/19/02.

CSE140 Final Review Xinyuan Wang 06/06/2019.

CSE 140 Lecture 16 System Designs

Presentation transcript:

CS 140 Lecture 18 Professor CK Cheng 12/3/02

Standard Sequential Modules 1.Register 2.Shift Register 3.Counter

3. Counter(Modulo-n counter) LD D Q TC Q (t+1) = (0, 0,.., 0)if CLR = 1 = Dif LD = 1 and CLR = 0 = (Q(t)+1)mod nif LD = 0, CNT = 1 and CLR = 0 = Q (t) if LD = 0, CNT = 0 and CLR = 0 CNT CLR CLK TC = 1 if Q (t) = n-1 and CNT = 1 = 0otherwise

Given a mod 16 counter, construct a mod-m counter (1 < m < 16) with AND, OR, NOT gates m = 6 Q 3 Q 2 Q 1 Q CLK CLR CNT D 3 D 2 D 1 D LD Q1Q1 Q0Q0 X Set LD = 1 when X = 1 and (Q 3 Q 2 Q 1 Q 0 ) = (0101)

Given a mod 16 counter, construct an a-to-b counter (0 < a < b < 15) 5 to 11 Q 3 Q 2 Q 1 Q 0 CLK CLR CNT D 3 D 2 D 1 D LD Q3Q3 Q0Q0 X Set LD = 1 when X = 1 and (Q 3 Q 2 Q 1 Q 0 ) = b (in this case, 1011) Q1Q1

Given a mod 16 counter, construct a counter with sequence Q 2 Q 1 Q 0 CLK CLR CNT D 2 D 1 D 0 LD Q 2’ Q0Q0 X Q2Q2 Q 0 Q 1 Q 0 Q 0’ When Q = 1, load D = 5 When Q = 6, load D = 2 When Q = 3, load D = 7

Q Q Q Q Q Q LD Id D D D D D D LD = Q 2’ Q 0 + Q 2 Q 0’ D 2 = Q 0 D 1 = Q 1 D 0 = Q 0 K Mapping LD and D, we get

Q Q Q Q Q Q LD Id D D D D D D D 2 = Q 0 D 1 = Q 1’ + Q 0 D 0 = Q 1’ Q 0 LD = Q 2’ Q 1’ + Q 2 Q 0 + Q 2 Q 1 K Mapping LD and D, we get Sequence LD = 1 D = 2 When Q(t) = 0 LD = 1 D = 7 When Q(t) = 5 LD = 1 D = 6 When Q(t) = 7 LD = 1 D = 0 When Q(t) = 6

Cascade Counter CNT LD TC CLK Q 7, Q 6, Q 5, Q 4 D 7, D 6, D 5, D 4 CNT LD TC CLK Q 3, Q 2, Q 1, Q 0 D 3, D 2, D 1, D 0 X

TC = 1 when X = 1, (Q 3, Q 2, Q 1, Q 0 ) = (1,1,1,1) (Q 7 (t+1) Q 6 (t+1) Q 5 (t+1) Q 4 (t+1) ) = (Q 7 (t) Q 6 (t) Q 5 (t) Q 4 (t) ) + 1 if TC = 1 & X = 1 The whole thing therefore can be viewed as a modulo 256 counter. (Q 3, Q 2, Q 1, Q 0 ) TC (Q 7, Q 6, Q 5, Q 4 )