ECE3801 Note Sheet NameProperty Associativea+(b+c)=(a+b)+c, a(bc) =(ab)c Distributivea+bc=(a+b)(a+c), a(b+c)=ab+ac. Also, Commutativea+b=b+a, ab=ba Idempotencea+a=a, a·a=a Identitya+1=1, a·0=0 Inverse Involution Unit, Zeroa ·1=a, a+0=a Absorptiona+ab=a, a(a+b)=a Logic Adjacency DeMorgen’s Laws Duality and Any valid expression is still valid if + and are swapped and 0 and 1 are swapped. Boolean Algebra, Etc. SRQQ1Q1 Result 00QQ’Q stored 0101Reset 1010Set 1101Unstable? S Q1Q1 Q R SR Latch D Q1Q1 Q C D Latch CDQQ1Q1 Result 00QQ’Q stored 01QQ’Q stored 1001Reset 1110Set D Q1Q1 Q > CLK Edge Trig. D Flip-Flop CLK DQQ1Q1 Result 00QQ’Q stored 01QQ’Q stored 001 Store 0 on rising clock 110 Store 1 on rising clock State Machine Types Sequencer: Current State  Output Current State  Next State Moore Machine: Current State  Output Current State, Input  Next State Mealy Machine: Current State, Input  Output Current State, Input  Next State ANALYSIS State Machine ANALYSIS Steps 1) Identify next state, output logic blocks, machine type. 2) Write output, next state equations. 3) Construct state transition table. 4) Construct state transition diagram. DESIGN State Machine DESIGN Steps 1) Draw state transition diagram. 2) State minimization; Number of flip-flops; Unused states. 3) State assignment and transition table. 4) Logic synthesis. 5) Implement. Edge Trig. JK Flip-Flop J Q1Q1 Q > CLK K JK CLK QQ1Q1 dd0Last QLast Q 1 dd1 Last Q Last Q 1 00 Last Q Last Q Last Q QQ+Q+ JK 000d 011d 10d1 11d0 Transition Key 

ARCHITECTURE Statements VHDL for Comb. Logic t PLH (ns)t PHL (ns) Device Number Device DescriptionTypMaxTypMax 74LS00Quad 2-Input NAND Gate LS02Quad 2-Input NOR Gate LS04Hex Inverter LS08Quad 2-Input AND Gate LS10Triple 3-Input NAND Gate LS11Triple 3-Input AND Gate LS20Dual 4-Input NAND Gate LS21Dual 4-Input AND Gate LS27Triple 3-Input NOR Gate LS308-Input NAND Gate LS32Quad 2-Input OR Gate AC Characteristics of Simple Gates in ns (T A =25 o C) [From: Motorola Fast and LS TTL Data (DL121/D, Rev 5)] Quine-McCluskey Minimization 1) Find all prime implicants using code word lists. 2) Minimize using cover table, etc. Exhaustive State Minimization 1) Create simplified state transition table (i.e., state assignments omitted). 2) Eliminate redundant states satisfying “sufficient” conditions (i.e., same outputs, next states for each input). 3) Construct implication chart: a) One box per pair of states. b) Eliminate state pairs with different output functions. c) Write implied next state equivalences. d) Eliminate implied equivalency conflicts. e) Read results. State Machine Timing (D Flip-Flops) 1) AND 2) AND 3) Synchronization Failure t r = metastable resolution time (usually t CLK – t ns – t setup ), f = flip-flop clock frequency, a = frequency of asynchronous input changes, , T o = constants. VHDL File Layout: Library Definitions ENTITY Declaration ARCHITECTURE IEEE 1164 Library LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Format ENTITY Ename IS PORT(name1, name2 : Mode Type; name3, … : Mode Type); END Ename; ARCHITECTURE Format ARCHITECTURE Aname OF Ename IS {Optional Definitions} BEGIN {Architecture Body} END Aname; Boolean: AND, OR, NAND, NOR, XOR, XNOR, NOT WHEN-ELSE: y<= “001” when a = “00” else “010” when a = “01” OR a = “10” else “100”; Selective Signal Assignment: WITH a SELECT y <= “010” WHEN “00”| “01”, “101” WHEN OTHERS;