Team M1 Enigma Machine Milestone April, 2006 Design Manager: Prateek Goenka Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka

Status Finished: –Behavioral Verilog and C simulation –Structural Verilog –Logic optimization –Module-level spice delay and power simulations –Floorplan –Top-level schematic testing In Progress: –Functional block layout –Simulation of functional blocks To do: –Global Layout –Testing –Simulation STATUS

Layout done:Layout Needed: GatesROM Muxes and RegistersRAM DFF, TFF FlipflopsFSM Add_Mod26 Wheel Counter Cells Wheel Counter Serial input 3-bit and 5-bit registers

Design Decisions Layout of Serial in registers Layout of 3-bit and 5-bit counter cells Updated layout of Wheel Counter Floorplan

Initial Floorplan

UPDATED FLOORPLAN

reg3bx8serialin

reg3bx8_serialin

Wheelregs_serialin

Wheel Counter Plan (Module layout and wire planning) 5-bit Counter Cell Data from counters Wheel Select Wheel Position 5-bit Counter Cell

countunit

wheelcounter

Questions?