© imec 2001 ARRM’01, Oct.17 Managing dynamic concurrent tasks in real-time multi-media systems Francky Catthoor, IMEC, Belgium

© imec 2001 ARRM’01, Oct.17 Goal of our research A methodology to map dynamic and concurrent real- time applications on an embedded multi-processor platform

© imec 2001 ARRM’01, Oct.17 MPEG4 JPEG Why are Applications becoming more dynamic and concurrent? The workload decreases but the tasks are dynamically created and their size is data dependent T1 T1’ T1 T2 T3 T4

© imec 2001 ARRM’01, Oct.17 MPEG-4 : multimedia spec = too huge to handle as 1 task => break up in many interacting tasks With this code my boss has to give me a raise!!! TASK1 h Cost(P) Exec.Time Divide-and-conquer approach of today leads to local solutions

© imec 2001 ARRM’01, Oct.17 This didn’t look so good after all??? TASK1 TASK2 TASK3 Processor 1 Global picture: ad hoc h h h t1 t2 t3 t1+t2+t3<T

© imec 2001 ARRM’01, Oct.17 TASK1 TASK2 TASK3 Processor 1 Global trade-offs with cost-performance curves h h h Luckily we have the Pareto approach! x x x t1n t2n t3n t1n+t2n+t3n<T

© imec 2001 ARRM’01, Oct.17 Outline Motivation: new challenges in system-level design Overview of TCM methodology Cost-efficient design-time scheduling

© imec 2001 ARRM’01, Oct.17 Maximize Quality Minimize Power Limited Resources Terminal QoS requires new approach CPU Bus access Mem. size Terminal ? Solution: Pareto curves 3D object Video object Tasks See session Multi-media 1

© imec 2001 ARRM’01, Oct.17 Very dynamic behaviour so worst-case realisation too costly

© imec 2001 ARRM’01, Oct.17 System design issues in IT-Application domain IN 622 Mb/s OUT 622 Mb/s 53 cycles Stringent real-time constraints Embedded system => cost Complex data sets Large and irregular dynamically allocated data Huge memory accesses Routing Record Packet Record FIFO 200 accesses data in ISR time data out routing reply out Processes Dynamic and concurrent processes Global/local control Non-deterministic events Network layer protocols (ATM, IP) Dynamic multi-media algorithms (MPEG4/7/21) Wireless/wired terminals (Internet, WLAN)

© imec 2001 ARRM’01, Oct.17 Executive Decoders Presenter Application Data Channel ALManager Flex Demux Service Data Channel Data Channel Data Channel Decoding Buffer Composition Memory BIFS Critical path OD msec Rendering Pre/post Decoding Pre/post writing Real-time constraints, tasks and data in the IM1-MPEG4 protocol

© imec 2001 ARRM’01, Oct.17 Why aren’t multi-processor platforms used now in embedded domains? Live from FZ-TV efficient mapping requires a very high design effort when done manually => need for a cost-sensitive real-time system compiler

© imec 2001 ARRM’01, Oct.17 Outline Motivation: new challenges in system-level design Overview of TCM methodology Cost-efficient design-time scheduling

© imec 2001 ARRM’01, Oct.17 Requirements of system level design approach AlgorithmsData Structures+ ARM IP 1 IP 2 RAMROM Architecture Processor architecture RAM ROM MMU custom logic DSP ROM micro processor TCM approach: ICPP’00, Kluwer book’99

© imec 2001 ARRM’01, Oct.17 TCM steps aim at removing the bottlenecks for better performance Optimized system specification Task-level system architecture Inter-task DTSE Task concurrency mngnt Task1 Task2 Task3 Inter-task interface refinement Task to processor assignment 1 Task/thread scheduling Task conc. Extraction/trafo Array-processor allocation Virtual Proc1 Virtual Proc2 2 Proc ICPP’00, Kluwer book’99

© imec 2001 ARRM’01, Oct.17 Static task scheduling cost time task1 cost time task2 cost time task3 platform Real-time constraints Run-time scheduler processor1 processor2 processor3 time platform Real-time constraints C/C++ specification of dynamic concurrent system Extraction of the gray-box model Task-level DTSE Concurrency improving transformations Memory architecture Real-time constraints

© imec 2001 ARRM’01, Oct.17 Outline Motivation: new challenges in system-level design Overview of TCM methodology Cost-efficient design-time scheduling

© imec 2001 ARRM’01, Oct.17 Reduce global system energy by task scheduling + assignment (e.g. 2-processor approach ) ARM Processor 1 V dd =1V V dd =3.3V ARM Processor 2 Task n Task 2 Task 1 Codes’01, J.of Sys.Arch, summer 2001

© imec 2001 ARRM’01, Oct.17 Trade-off between time budget (period/latency) and cost (e.g.energy) leads to Pareto curves Time Cost CB1CB2CB3CB4CB5CB6 Processor alloc/assign and scheduling alternatives for code version 1 x x x x Non-optimal points

© imec 2001 ARRM’01, Oct.17 TCM transformations on application model shift Pareto curve to origin Bottleneck of case 1 Scheduling alternatives for case 1 Transformations shift the Pareto Curve –Decrease cost for same Time-Budget –Increase performance for same Cost-Budget New curve for case 2 TCM trafo Energy Time Budget

© imec 2001 ARRM’01, Oct.17 Comparison for original and transformed IM1 graphs on 2 processors with different Vdd original Transformed

© imec 2001 ARRM’01, Oct.17 Comparison between different processor platforms Combination 2 Combination 3 (Global Pareto curve) Global Pareto curve

© imec 2001 ARRM’01, Oct.17 Comparison of genetic algorithm (GA) and heuristic task scheduling results

© imec 2001 ARRM’01, Oct.17 Why run-time scheduler?(I) Design-time Scheduler + Predictability- Schedulability for - Flexibility dynamic events + Run time complexity+ Optimization Run-time Scheduler - Predictability+ Schedulability for + Flexibility dynamic events - Run time complexity- Optimization

© imec 2001 ARRM’01, Oct.17 Overall solution: combination of design- and run-time schedulers Cases’00, Design&Test- Sep.’ Design-time Scheduling AB Design-time scheduling: at compile time, exploring all the optimization possibility Run-time Scheduling 1AB32 Run-time scheduling: at run time, providing flexibility and dynamic control at low cost as part of synthesized RTOS

© imec 2001 ARRM’01, Oct.17 Main messages Embedded multi-media applications are becoming very dynamic and concurrent in nature => RTOS essential Task Concurrency Management approach provides the flexibility and optimization possibility while limiting the run time computation complexity A multiprocessor platform with different working voltages potentially provides an energy saving solution Application-specific run-time scheduling technique combined with design-time scheduling to provide cost- performance Pareto-curve essential for effective solution