Group M3 Nick Marwaha Craig LeVan Jacob Thomas Darren Shultz Project Manager: Zachary Menegakis March 23, 2005 MILESTONE 9 Chip level LVS DSP 'Swiss Army Knife' Overall Project Objective: General Purpose Digital Signal Processing Chip

STATUS Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (Done) Gate Level Design (100%) Layout (91%) To Be Done LVS of Entire FP Multiplier Complete Top Level Wiring of FP Adder Global Wiring Improved, smarter floor plan Shave (Jake) Sleep (All)

DESIGN DECISIONS Floorplanning, due to changes in design Booth Wallace Tree Multiplier Comp3_2 block Had to choose between a rectangular or more square and shorter implementation.

LAYOUT – FP Multiplier Currently, debugging few remaining LVS errors This 12 bit Metal4 bus is here only to show possible routing channel to be used in Global Routing.

LAYOUT – FP Adder Left Shifter Differencer Most of the major blocks are done; top level wiring remains. Here are example blocks.

FLOORPLAN Still Under Construction Due to FP Adder

SIMULATIONS Craig is currently MIA due to a broken bone and medication side effects. All simulation results are with him wherever he is right now. Last we heard he was going to the doctor.

LAYER MASKS

TOP LEVEL SCHEMATIC Top Level Schematic is done completely (after adjusting for DSP discoveries), and currently undergoing verification.

SIZE ESTIMATES Transistor Count: ~30K, should have exact # tonight Final Area: ~500x250 µm Aspect Ratio: ~2:1

PROBLEMS & QUESTIONS Top Level Wiring of the FP Adder Final Floorplan Soft IP – need some further research with DSP TAs regarding imaginary numbers