המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Full sniffer system for PCIe Midterm presentation Performed by: Omer Blecher, Roy Fridman Instructor: Boaz Mizrachi

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Agenda Main Goal and Project A Goals Current status System characterization Long Range modifications First step modifications completed tasks Future tasks and current semester plan

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Main Goal Providing a fully operational Sniffer who is able to connect on a PCIe bus,stream a PCIe packet to a analyzer and perform a complete packet analysis of the signals in an analysis and control PC. General purpose of project utilizing/modifying existing components of the system and creating missing components for (full system integration).

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Project A goals(1/2) Gaining extensive theoretical knowledge of the systems current building blocks. Learning the platforms/protocols and algorithms needed on a wide perspective – 1.PCI express electrical definitions and protocol requirements. 2.8/10 bit coding. 3.UART connection. 4.RocketIO transceivers. 5.s/w and h/w platform design tools such as PPC,HDL designer, Xilinx platform studio.

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Project A goals(2/2) Creating a fully detailed system characterization (h/w, s/w and more) including future s/w and hardware modification and algorithms that will be implemented on project B. full system operation and “hello world” modification: 1. Hardware: moving the TGA current design from the FF672 evaluation board to the FF1152 and confirming that the design is fully active on the new board (will be elaborated ). 2. software: creating a flow that its main purpose is to display a packet (will be elaborated ).

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory PC FF672 Crossbar Board Passive Trace Board Test 2.5G cables 2.5G Management cable Current status (General)

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Current status (Hardware) CTG – creates a burst of Randomized packet transmission with defined parameter of min and max values in the PGP BRAM. CTA – received the sent burst after alignment, saves only the damaged packet in the TSS BRAM. Data padding Depends on min and max parameters Time XX Start K char Stamp End K char X Stamp XX

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Current status (Software) Pic (microcontroller)- configure M x34 Crosspoint switch, write and read data from the EEPROM, Turn on or off LEDs,enable and disable dipswitches, read status bits from the card and write control bits Power PC- turn on LEDs, read status of dipswitches and push buttons, read and write from the TSS and PGP memories, and send command to the pic. Experiment GUI- not relevant because it will be recreated to suit different needs

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Features and utilization in S/W: Displaying packets in logical sectors Traffic Summary Link Tracker Timing calculations Bus utilization Advanced Search for specific packets System characterization (Top down)

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Displaying packets in logical sectors (1/5) There are 4 PCIe transaction types: Memory transaction. I/O transaction. Message transaction. Configuration transaction. I/O Write Request I/O Read Request I/O Write Completion Interrupt signaling Error signaling Power management I/O Read Completion Memory Write Request Memory Read Request Memory Write Completion Memory Read Completion Configuration Write Request Configuration Read Request Configuration Write Completion Configuration Read Completion

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Displaying packets in logical sectors (2/5) Basic display method:

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Serial number: every packet gets a number which indicates the order of the arrival. TLP: the sequence number which was given to the packet by the DLLP. ECRC: Every packet can have ECRC- CRC calculation which created in the TLP. LCRC: Every packet has a LCRC- CRC calculation which created in the DLLP. Time stamp: Every packet gets a time stamp- indication of the arrival time. Displaying packets in logical sectors (3/5) General:

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Type of transaction: Memory, I/O,Configuration and Message. Operation: Read or Write. RequestID: The I.D number of the device which create the request. Tag: Field to identify the request. Byte Enable: Indicates which byte of the DWord is a valid data bytes, and which byte is “Padding” bytes. Address: The register which we want to read/write from/to. Data: The intended data (optional). Displaying packets in logical sectors (4/5) Request Packets:

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Completion I.D: The I.D number of the device which send a complition. Completion Status: Indication if the device perform a successful completion. Byte Count: Indication of how many packets are left to complete memory read request. RequestID: The I.D number of the device which create the request. Tag: Field to identify the origin of the request Low Address: Byte address of the first enabled byte of data. Displaying packets in logical sectors (5/5) completion Packets:

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Traffic Summary (1/2) The s/w will consist of 5 detailed summeries: General packet summery: Show a summery of of all packets Group by valid and invalid packets. TLP packet summery: Show a summary of all the packets that origin from the TLP, group by all type of TLP types. Request summery: Show a summery of all the request packets, group by the different requester I.D. Completion summery: Show a summery of all the completion packets, group by the different completer I.D. Error summery: Show a summery of all the damaged packets, group by all types of error.

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Traffic Summary (2/2) Display method of 2 root summaries: Error Type Error Type Description Bad ECRC’s Bad ECRC’s Indication of a bad transmission from the transaction layer Bad LCRC’s Indication of bad transmission from the data link layer Alignment Error The packet isn’t aligned correctly Bad packet length Invalid length of packet End of a bad packet Get the code K30.7 which represent an invalid packet TLP Type TLP Type Description Memory Request Transfer data from or to a memory mapped location I/O Request Transfer data from or to an I/O mapped location Configuration request Device configuration/setup, Read or write a request or a completion Message request From event signaling mechanism to general purpose messaging Completion packet A reply packet for request packets

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Link Tracker (1/2) Presenting the arrival of packets according to a time table: The first column is for the time since the beginning of sampling packets. The second column shows the number of packet. The third column shows packets that arrive from the graphic card. The forth column shows packets that arrive from the mother-board.

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Link Tracker (2/2) Basic display method:

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Timing calculations Calculate efficient bus width in an interval of time Choosing the start time of the calculation: Choosing the end time of calculation: Presenting the total time: Presenting the bit rate of the upstream and the bit rate of the down stream: *** Time is measured between different intervals that will be defined by the user.

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Bus utilization Presenting a diagram of number of packets every 1 micro second:

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Advanced Search for specific packets (1/2) Configure the analyzer to capture a specific range of packets: The configuration is made by sending a mask to the modified TGA: The mask contain a sequence of bits for h/w filtering use. the main idea is that the user defines a search and a mask is created accordingly in the PC. A predefined h/w block added o the TGA will use the mask to filter wanted packets. Search display method: after the receiving of the packets, we will show on the screen only chosen packet or range of packets.

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Advanced Search for specific packets (2/2) STP (K27.7) R|Fmt|TypeContinuation of the header Sequence Number R|Fmt|Type Type Configuration I/O Request The chosen byte (first byte of the header)

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Long range modifications Classifier – A component with basic logic abilities of receiving a word of 32 bits (A) and compare a selected stream of bits in A to a known “mask” (B) and perform the following logic operations: A=B? A B? A<>B? DRAM controller+buffer - interface with DRAM is needed for minimizing trade off problem with quality of filtering and allowing wanted features that are mapped in the system characterization.

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Software first step modification Time Start K char End K char XXX

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware first step modification Full design relocation

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Completed tasks System characterization - s/w and h/w systems current building block extensive review PCI express electrical definitions and protocol requirements. 8/10 bit coding. UART connection. RocketIO transceivers.

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Future tasks and current semester plan weekly minimal hours each – 1. until 6/4/06: 36 (3 days) 2. After 6/4/06: 18 (day and a half) Detailed distribution

המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Detailed time distribution  S/W: 1.Design environment review (c++) 4 weeks 2. Basic GUI creation 1 week 3. System interface with FF672 and FF week 4.Integration (first step s/w modification) 1 week  H/W: 1. Low level system designs 5 weeks 2. first step h/w modification 3 weeks